ASIC Implementation of a Systolic Array for Image Processing

1
ASIC Implementation of a Systolic Array for Image
Processing
United Arab Emirates University College of
Engineering Graduation Projects Unit

• Alia Obaid Al-Zaabi
  199904083
• Slama Obaid Al-Ketbi
  199903925
• Shaikha Ahmad
  199902234
• Fatima Ahmad
  200235050

2
Presentation Layout

• Objective
• Introduction
• Project specifications
• How the system works?
• System components
• Design and simulation results
• Conclusion

3
Objective

• Design and implementation of a systolic array
  that performs different operations on images

4
Introduction

• ASIC
• Application Specific Integrated Circuit.
• very fast data transfers.
• Where it can be used?
• Medical images
• Geostationary satellite images

5
Introduction

• Systolic array
• An array of neighbors processors connected
  together in a rectangular form.

6
Project specifications
Each node of the array should perform four
different operations on the image
7
Project specifications

• Implementation technology
• 0.35 micron CMOS technology

8
The components of the system

• The control logic circuit
• Registers
• Inverter
• Adder
• Comparator
• Multiplexer

9
How the system works?
Our system
Inputs 00
011011
User
Captured Picture
10
How the system works?
How the System works
Our system
Input 10
011011
User
Invert the colors
Captured Picture
11
How the system works?
How the System works
Our system
Inputs 01
011011
User enters the inputs to the system
Gray
Captured Picture
if the operand is less than the input send the
Operand to the output
12
The project components

• Control logic Circuit

13
The project components
Control logic Circuit

• The Truth table of the control logic block

14
The project components
Control logic Circuit
The K-map method to get the function of So
So B1(CBo' C'Bo) BoB1'
The K-map method to get the function of S1
S1 B1
15
The project components
Control logic Circuit
The control logic block
16
Transistor implementation of the Control Logic
Circuit in LASI 7
17
The project components

• Registers (Input , Operand Output).
• 8 bit register contains 8 D-flip flops.
• Type
• Edge Triggered D-flip flop

18
The D flip flop
The timing relationship between (clock, input and
output)
19
The design of D-flip flop
The one bit D-flip flop using NAND gates
20
Transistor implementation of the 8-bit output
Register in LASI 7

• Parallel in Series out Shift Register.

8-bit output Register
21
Transistor implementation of the 8-bit input
Register in LASI 7

• Series in Parallel out Shift Register.

22
The project components

• Inverter Two transistors PMOS and NMOS

8 bit inverter
CMOS inverter
23
The project components
The adder
The truth table of the adder
The Binary Full adder
The output is high if and only if one or all of
the inputs are high.
24
The adder
Two types
static CMOS Adder
Mirror Adder
25
The project components
Adder

• The Ripple Adder

26
Transistor implementation of the adder in LASI 7

• Eight 1-bit Adder connected in series.

1-bit Adder
8-bit Adder
27
The project components
The comparator
The truth table of the comparator
28
Transistor implementation of the comparator in
LASI 7
1 bit Comparator
8 bit Comparator
29
The project components
The Multiplexer

• Three 2X1 Multiplexer.
• Pass transistor logic.

30
Pass-transistor logic MUX
31
Transistor implementation of the Multiplexer in
LASI7
1-bit Multiplexer
8-bit Multiplexer
32
The simulation result of the Control Logic
Circuit
The truth table
33
The simulation result of the input Register
The truth table of D-Flip Flop
34
The simulation result of the output Register
The truth table of D-Flip Flop
35
Simulation Results
The simulation result of the Inverter
The truth table
36
The simulation result of the Adder
The truth table
37
The simulation result of the Comparator
The truth table
38
The simulation result of the Multiplexer
The truth table
The truth table
39
The propagation delay

• The propagation delay tP is defined as the
  average of the low-to-high propagation delay
  (tPLH) and the high-to-low propagation delay
  (tPHL)

• tP 1/2( tPLH tPHL )

40
The propagation delay of the Inverter
TpHL 3.8835 ps TpLH 0.00935 ns Tp (TpHL
TpLH) /2 0.00661675 ns
41
Propagation delay of individual blocks
42
Critical path
43
System propagation delay and clock Frequency
TP1 0.174755 ns TP2 0.182 ns
System Delay Tp 0.468775 ns The system
clock frequency 2.133 GHz.
44
Cost Estimation

• Visit MOSIS web site.
• Check MOSIS price list.
• Calculate project area.
• Project Area will not exceed 10mm2

45
MOSIS list price for the 0.35 Micron
46
MOSIS list price for Plastic packaging
   
47
Design Rule Checking Service Testing prices
48
The total estimation cost 12,42050025005200
20600
49
Conclusion

• The objectives of this project were achieved at
  the end of phase one
• All the components of the system were designed
  and simulated.
• The time delay for each components was
  calculated.
• The critical path, was the path through the
  Adder.
• The system clock frequency was calculated from
  the system delay and it is equal to 2.13 GHz.

50

• Any Questions?