Measurements on preproduction wafers at Udine

1
Measurements on pre-production wafers at Udine

• Presented by M. Cobal
• on behalf of the Udine group
• Pixel Week December 2001

2
Measured Wafers

• CiS

• Tesla

- 4456-21 - 4456-23 - 4457-23 - 4458-21
- A31-02 - A31-07 - A31-08 - A31-12
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Outline

• Tiles and diodes with guard ring
• IV measurements
• CV measurements
• tile conformity
• SCs and MCs yield
• Visual inspection
• ID marking correctness
• visual inspection
• mask alignment

4
IV measurements

• This time, taken with 2-side chuck
• Temperature corrections applied

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Diode position
16
n side
17
6
IV meas. on diode 17 (CiS)
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IV meas. on diode 17 (Tesla)
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Quality Control Parameters

• Tile conformity criteria
• Vbd(tile)gt Vop(diode)
• SlopeI(tile _at_ Vop)/I(tile _at_ Vop-50)lt2
• Vopmax(Vdep50,150)
• Need to measure Vdep

9
Capacitance offset
10
CV results
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CV results
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Determination of Vdep and Vop

• - Measurements lie within
• 65 V lt Vdeplt 100 V
• - Procedure specs demanded
• 30 V lt Vdep lt 120 V
• - For all wafers Vdep lt100 V
• Vop max(Vdep50,150) 150 V

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Determination of Cdep and r

• Cdep is between 1.7-4.2 (4.5-5.6) pF for CIS
  (Tesla)
• Determined as CdepC(Vdep)-Coffset
• DCoffset of order of 0.2-0.7 pF (for positive
  polarity)
• r lies within 2.1-3.3 kWcm
• conformity range is 2-5 kWcm

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Tile results (CiS)

• Results in agreement with CIS
• 2 wafers with 2 good tiles
• 2 wafers with 3 good tiles
• wafer 4456-21 with
• Slope (Tile 1) 3.58

15
SC and MC yield (CiS)

• SCs 6 x 4 24
• 5 are bad (Vbdlt150)
• 79 are good

• MCs 4 x 4 16
• 1 is bad (Vbdlt150)
• 94 are good

16
Tile results (Tesla)

• Disagreement for 1 Wafer out of 4
• Wafer A31-12
• Slope(Tile 2)
• Our measure Tesla
• 2.08 1.85

17
SC and MC yield (Tesla)

• SCs 6 x 424
• 1 is bad (Vbdlt150)
• 96 are good

• MCs 4 x 416
• 4 are bad (Vbdlt150)
• 75 are good

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Scratch pad marking (CIS)

• 2- and 3-good-tile wafers
• TILES all 4 pads marked.
• SCs only 1 of the 2 pads marked (lower one).
• All markings are correct.

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Scratch pad marking (Tesla)

• 2 and 3 good tiles wafers
• TILES only 2 out of 4 pads marked.
• SCs only 1 of the 2 pads marked (lower one).
• All markings are correct.

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Visual Inspection (CiS)

• 4456-21
• n-side Tile 2, small scratch (6 pixels)
• 16, extended scratch (superficial)
• 4456-23
• n-side Tile 1, one pixel defective
• Tile 2,
• Tile 3, three pixels defective
• 22, extended scratch (superficial)
• MC13, one pixel larger

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Visual Inspection (Tesla)

• A31-02
• p-side 17, small scratch
• 12, small scratch
• A31-08
• n-side 19, extended scratch
• p-side bad end of the three top structures

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Scratch
23
Mask alignment
vernier
Goal Measure 2 mm misalignment Use Nikon
Optiphot 150 _at_ 200-500 X
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Mask alignment (CiS)

• Good contrast
• For vertical vernier, 4 vs 5 bars

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Mask alignment (CiS)

• Out of specifications
• Wafer 4457-23 n-side, left pad, 4th hor.
• right pad, 4th hor.
• p-side, right pad, 4th hor.
• Wafer 4456-23 n-side, right pad, 4th hor.
• p-side, right pad,
  4th hor.
• Wafer 4458-21 n-side, left pad, 4th hor.
• right pad, 4th hor.
• p-side, right pad, 4th hor.

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Mask alignment (Tesla)

• Quite bad contrast for all the vernier
• All 3rd vernier are missing
• All the 4th vernier are badly printed

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Mask alignment (Tesla)

• Out of specifications
• Wafer A31-02 p-side, right pad, 1st vert.
• Wafer A31-07 p-side, right pad, 1st vert.
• Wafer A31-12 p-side, left pad, 4th vert.

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Database

• The new wafers (both CiS and Tesla) have been
• already inserted in the database
• IV measurements will be added very soon
• For CV measurements, needs to understand
• better