Sensor Signal Processing

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Sensor Signal Processing

• Ryan Miller
• STARLight Electrical Engineer
• [phone]
• rpmiller_at_umich.edu

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Overview

• Sensor Requirements
• Signal Processing Chain Overview
• Sampling
• Digital Signal Processing
• Data Formatting and Rates
• Hardware Overview
• Power Summary

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Sensor Requirements

• Sample 10 1.413 GHz, band-limited signals
• lt 20 ps sample to sample jitter
• lt 6.7 ns channel to channel sample skew
• 3-bit digitization
• Digitally filter the data to ease requirements on
  analog filter
• Recover the Inphase and Quadrature components of
  each of the 10 signals
• Calculate digitization statistics for each ADC
• Allow gain/offset adjustment for each ADC to
  optimize 3-bit conversion
• Monitor critical receiver temperatures
• Provide thermal control electronics

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System Block Diagram
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Signal Processing Chain
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Sampling

• Minimum sample rate (Fs) is 2 times bandwidth
• Bandwidth must include the analog Pre-Sample
  Filter skirts
• Sample rate must be selected so that sampled data
  is aliased to Fs/4 for quadrature demodulation
• Since the Band Definition Filter is digital,
  would like to relax the analog Pre-Sample Filter
  specification
• Wider Bandwidth
• Gentler Roll-off/Fewer Poles

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Sample Rate Calculations
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Possible Sample Rates

• Nyquist Sample Rate 72 MHz
• Fs/4 F0/(2M-1)
• Minimum sample rate 73.4 MHz
• Fs/4 18.35 MHz
• Pre-Sample Filter BW limited to 36.7 MHz
• Desired sample rate 102.8 MHz
• Fs/4 25.7 MHz
• Pre-Sample Filter BW can be 51 MHz
• After digital filtering and Quadrature Demod, can
  decimate by a factor of 2

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Results of Sampling at 102.8 MHz
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The Next Step

• Digital Filter before Quadrature Demodulation
• PRO
• Only need 10 filters
• CON
• Must operate at 100 MHz
• Filter must be band-pass
• Quadrature Demodulation before Digital Filter
• PRO
• Reduces data rate by factor of 2
• Digital Filter becomes low-pass
• Quadrature Demod includes FIRs might be able to
  combine
• CON
• Need 20 digital filters

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Digital Filtering then Quad Demod.

• Reduced hardware complexity
• Fewer filters less hardware
• Band-pass FIR may require more stages, but not
  twice as many
• Speed
• Depends on FPGA specifications and implementation
• I/O is specd at 300 MHz
• Implementation is flexible, Transposed form FIR
  relies on fast adders
• Xilnx FPGAs have built in adder support
• 64-bit ADD specd at 150 MHz

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Digital Filtering First

• Define the final signal bandwidth using a digital
  filter
• Allows identical filters to be used on all
  channels
• Allows some relaxation of analog Pre-Sample
  Filter and minimizes channel to channel matching
  requirements
• Requires at least 30 stage bandpass FIR
• For 30 Stage, 16-bit (approx.)
• 3016303 570 Registers/Filter
• 10 Filters require 5700 registers
• Xilinx XCV600 has over 15,000 registers

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Transposed Form FIR Filter

• Samples go to all taps simultaneously
• Tap coefficient multiplies implemented with
  lookups
• All adders are 2-input Reduces cascading,
  increases speed

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Matlab Designed Quantized FIR

• Used Matlab Filter Design Toolbox
• Designed for quantized 10-bit coefficients
• Sample filter design with 31 taps
• Filter is symmetric
• Filter is linear phase
• Can save hardware since half the coefficients are
  zero

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Quantized Filter Response
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Quadrature Demodulation

• Mix digitized signal with sine and cosine
  (0,1,0,-1,)
• Filter the results
• Produces the Inphase and Quadrature components
• Each component is at half the sample rate

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I Q Recovery Implementation

• The mixing operation is combined with the FIR
  operation and replaced with a multiplexor
• The Inphase channel is simply delayed
• The Quadrature channel is filtered with a
  simplified Hilbert Transform FIR (90 phase shift)

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Sampling Summary

• Resulting 12 MHz bandwidth of I and Q channels
  requires only 24 MHz Sample rate per channel
  (25.7 MHz)

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Other Sensor Functions

• Channel Totalizing Counters
• 7 counters for each channel
• Count occurrences of each binary value over the
  integration period
• Housekeeping Data Collection
• Up to 6 receiver temperature monitors
• Thermal Control
• PWM plus drive electronics for heater in each
  receiver

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Sensor Data Rates

• 73.4 MHz sampling
• Raw bit rate 10 channels 3 bits 73.4 MHz
  2.2 Gbps
• After I/Q Demod 20 channels 3 bits 36.7 MHz
  2.2 Gbps
• 102.8 MHz sampling
• Raw bit rate 10 channels 3 bits 102.8 MHz
  3.1 Gbps
• After I/Q Demod 20 channels 3 bits 25.7 MHz
  1.5 Gbps
• Totalizer Output (one second integration)
• 10 channels 7 bins/channel 29 bits per bin
  2030 bits/sec
• Temperature Data
• 10 channels 6 temps/channel 16 bits/temp
  960 bits/sec

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Hardware Overview
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Sensor Data Acquisition
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A/D Converter Comparison
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SPT 7610 A/D Selected

• Power
• Lowest power of the 3 available
• Package
• Flat-pack package
• Maxim only available in Ball-Grid Array Package
• Temperature Range
• Available in Industrial Temp. Range (-40 to 85C)
• Maxim only available in Commercial Temp. Range (0
  to 70C)
• Availability
• Parts in-house
• Atmel 888.00 ea, Minimum order of 4, 16-week
  lead time

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Sensor Control Board
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Sensor Housekeeping Data Acquisition

• Low-speed 16-bit A/D Converter
• Interface electronics for up to 6 thermistors
• Reference electronics to improve accuracy
• Low-speed data will be time-tagged and read on
  demand by the Control Computer through the Status
  and Control Interface

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Sensor Power Summary

• Sensor Data Acquisition Board (x 10 boards, not
  including Receiver)
• 7.0 Watts Maximum
• 5.4 Watts Typical
• Sensor Control Board
• 6.0 Watts Maximum

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FPGA Tradeoffs

• Altera
• PRO
• In-house experience
• High-speec, high-density devices
• CON
• No extended temperature range devices
• Large devices in non-BGA packages have limited
  I/O capabilities
• More expensive tools
• Xilinx ? Selected
• PRO
• High-speed, high-density devices
• Devices support many I/O standards including LVDS
  and LVPECL
• Available in extended temperature range versions
• Less expensive tools (although ModelSim simulator
  is extra)
• CON
• ?

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Design Status

• Sensor Data Acquisition Board
• Prototype and Flight boards are identical
• Schematic 75 complete
• Most components ordered and received
• FPGA Design 10 complete
• Sensor Control Board
• Prototype and Flight boards are identical
• Schematic 25 complete
• Most components ordered and received
• FPGA Design 10 complete
• Development Tools
• Schematic capture McCad
• FPGA Development Xilinx ISE ModelSim
• Analysis Matlab, Simulink

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Schedule