ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Dynamic Power

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ELEC 5970-001/6970-001(Fall 2005)Special Topics
in Electrical EngineeringLow-Power Design of
Electronic CircuitsDynamic Power

• Vishwani D. Agrawal
• James J. Danaher Professor
• Department of Electrical and Computer Engineering
• Auburn University, Auburn, AL 36849
• http//www.eng.auburn.edu/vagrawal
• vagrawal_at_eng.auburn.edu

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CMOS Dynamic Power
Dynamic Power S 0.5 ai fclk CLi
VDD2 All gates i 0.5 a fclk CL
VDD2 a01 fclk CL VDD2 where a average
gate activity factor a01 0.5a, average 0?1
trans. fclk clock frequency CL total load
capacitance VDD supply voltage
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Example 0.25µm CMOS Chip

• f 500MHz
• Average capacitance 15 fF/gate
• VDD 2.5V
• 106 gates
• Power a01 f CL VDD2
• a01500106(1510-15106) 2.52
• 46.9W, for a01 1.0

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Signal Activity, a
T1/f
Clock
a01 1.0
a01 0.5
Comb. signals
a01 0.5
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Reducing Dynamic Power

• Dynamic power reduction is
• Quadratic with reduction of supply voltage
• Linear with reduction of capacitance

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0.25µm CMOS Inverter, VDD 2.5V
0 -4 -8 -12 -16 -20
2.5 2.0 1.5 1.0 0.5 0
Gain dVout /dVin
Vout (V)
0 0.5 1.0 1.5 2.0 2.5
0 0.5 1.0 1.5 2.0 2.5
Vin (V)
Vin (V)
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0.25µm CMOS Inverter, VDD lt 2.5V
Similar to analog amplifier
2.5 2.0 1.5 1.0 0.5 0
0.2 0.15 0.1 0.05 0
Vout (V)
Vout (V)
Vth 0.4 V
0 0.5 1.0 1.5 2.0 2.5
0 0.05 0.1 0.15 0.2
Vin (V)
Gain -1
Vin (V)
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Low Voltage Operation (VDD gt Vth)

• Reduced dissipation, increased delay.
• Operation sensitive to variations in device
  parameters like Vth .
• Reduced signal swing reduces internal noise
  (crosstalk), increases sensitivity to external
  noise.

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Impact of VDD on Performance
CLVDD Inverter delay K ------- ,
Power CLVDD2 (VDD Vth )a
40 30 20 10 0
Delay (ns)
Power Delay
0.4V 1.45V 2.5V VDD
VDDVth
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Optimum Power Delay
VDD3 Power Delay, PD constant
------- (VDD Vth)a For minimum
power-delay product, d(PD)/dVDD 0 (VDD
Vth)a 3VDD2 VDD3 a (VDD Vth)a
1 0 (VDD Vth)2a
3VDD 3Vth a VDD VDD 3 Vth / (3
a)
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Optimum Power Delay (Cont.)
For minimum power-delay product, d(PD)/dVDD
0 3Vth VDD --- 3 a For long
channel devices, a 2, VDD 3Vth For very
short channel devices, a 1, VDD 1.5Vth
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Very Low Voltage Operation

• VDD lt Vth
• Operation via subthreshold current.
• Small currents have long charging and discharging
  times very slow speed.
• Increasing sensitivity to thermal noise.

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Lower Bound on VDD

• For proper operation of gate, maximum gain (for
  Vin VDD/2) should be greater than 1.
• Gain - (1/n)exp(VDD / 2FT) 1 - 1
• n 1.5
• FT kT/q 25 mV at room temperature
• VDD 48 mV
• VDDmin gt 2 to 4 times kT/q or 50 to 100 mV at
  room temperature (27oC)
• Ref. J. M. Rabaey, A. Chandrakasan and B.
  Nikolic, Digital Integrated Circuits, A Design
  Perspective, Second Edition, Upper Saddle River,
  New Jersey Pearson Education, 2003, Chapter 5.

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Capacitance Reduction

• Transistor sizing for
• Performance
• Power

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Basics of Sizing (S Scale Factor)

• Sizing a gate by factor S means all transistors
  in that gate have their widths W changed to WS.
  Lengths (L) of transistors is left unchanged.
• On resistance of the scaled transistor is reduced
  as 1/S
• Gate capacitance is scaled as S
• Next we consider the delay and power of the
  original and scaled gates.

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A Standard Inverter, S 1

• Cg input capacitance
• Req on resistance
• Cint intrinsic output capacitance Cg

Cg
CL
Cint
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Transistor Sizing for Performance

• Problem If we increase W/L to make the charging
  or discharging of load capacitance faster, then
  the increased W increases the load for the
  driving gate

Slower charging More power
Faster charging
Req /S
CinCg
CLSCg
Increase W for faster charging of CL
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Delay of a CMOS Gate
Gate capacitance
Intrinsic capacitance
CMOS gate
Cint
CL
Propagation delay through the gate tp K 0.69
Req (Cint CL) K 0.69 ReqCg (1 CL
/Cg) tp0 (1 CL /Cg) where K depends upon
VDD, Vth, etc.
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Req , Cg , Cint , and Width Sizing

• Req equivalent resistance of on transistor,
  proportional to L/W scales as 1/S, S width
  sizing factor
• Cg gate capacitance, proportional to CoxWL
  scales as S
• Cint intrinsic output capacitance Cg , for
  submicron processes
• tp0 intrinsic delay K 0.69ReqCg ,
  independent of sizing

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Effective Fan-out, F

• Effective fan-out is defined as the ratio between
  the external load capacitance and the input
  capacitance
• F CL /Cg
• tp tp0 (1 F )

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Sizing Through an Inverter Chain
1
2
N
CL
Cg2 f2 Cg1 tp1 tp0 (1 Cg2/Cg1) tp2 tp0
(1 Cg3/Cg2) N N tp S tpj tp0 S (1
Cgj1/Cgj) j1 j1
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Minimum Delay Sizing
Equate partial derivatives of tp with respect to
Cgj to 0, for all j 1/Cg1 Cg3 /Cg22 0, etc.
or Cg22 Cg1 Cg3, etc. or Cg2/Cg1 Cg3
/Cg2, etc. i.e., all stages are sized up by the
same factor f with respect to the preceding
stage CL/Cg1 F f N, tp Ntp0(1 F1/N )
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Minimum Delay Sizing
Equate partial derivatives of tp with respect to
N to 0 dNtp0(1 F1/N) ---------
0 dN i.e., F1/N F1/N(ln F)/N 0, or ln (f
N) N or ln f 1 ? f e 2.7 and N ln F
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Further Reading
B. S. Cherkauer and E. G. Friedman, A Unified
Design Methodology for CMOS Tapered Buffers,
IEEE Trans. VLSI Systems, vol. 3, no. 1, pp.
99-111, March 1995.
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Sizing for Energy Minimization
Main idea For a given circuit, reduce energy
consumption by reducing the supply voltage. This
will increase delay. Compensate the delay
increase by transistor sizing. Ref J. M.
Rabaey, A. Chandrakasan and B. Nikolic, Digital
Integrated Circuits, Second Edition, Upper
Saddle River, New Jersey Pearson Education, 2003.
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Sizing for Energy Minimization
f
1
Minimum sized gate
Req
Req /f
tp tp0 (1 f ) (1 F/f ) tp0(2 f F/f
) F CL/Cg1 , effective fan-out tp0 VDD
/(VDD Vth) for short channel Energy
dissipation, E VDD2Cg1(2 2f F )
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Holding Delay Constant

• Reference circuit f 1, supply voltage Vref
• Size the circuit such that the delay of the new
  circuit is smaller than or equal to the reference
  circuit
• tp tp0 (2fF/f ) VDD Vref - Vth 2fF/f
• -- -------- -- ---- ----- 1
• tpref tp0ref (3 F ) Vref VDD- Vth
  3F

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Supply Voltage Vs. Sizing
3.5 3.0 2.5 2.0 1.5 1.0
Vref 2.5V Vth 0.5V
F1
2
5
fopt vF
VDD (volts)
10
1 2 3 4 5
6 f
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Energy
E VDD2 2 2f F -- --- ------ Eref
Vref2 4 F
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Normalized Energy Vs. Sizing
1.5 1.0 0.5
Vref 2.5V Vth 0.5V
F1
2
5
fopt vF
Normalized Energy
10
1 2 3 4 5
6 f
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Summary

• Device sizing combined with supply voltage
  reduction reduces energy consumption.
• For large fan-out energy reduction by a factor of
  10 is possible.
• An exception is F 1 case, where the minimum
  size device is also the most effective one.
• Oversizing the devices increases energy
  consumption.