ELEC 59700016970001 Fall 2005 Special Topics in Electrical Engineering LowPower Design of Electronic

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ELEC 5970-001/6970-001 (Fall 2005)Special Topics
in Electrical EngineeringLow-Power Design of
Electronic CircuitsIntroduction

• Vishwani D. Agrawal
• James J. Danaher Professor
• Department of Electrical and Computer Engineering
• Auburn University
• http//www.eng.auburn.edu/vagrawal
• vagrawal_at_eng.auburn.edu

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Course Objective

• Low-power is a current need in VLSI design.
• Learn basic ideas, concepts and methods.
• Gain hands-on experience.

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Low-Power Design

• Design practices that reduce power consumption at
  least by one order of magnitude in practice 50
  reduction is often acceptable.
• General topics
• Algorithms and architectures
• High-level and software techniques
• Gate and circuit-level methods
• Power estimation techniques
• Test power

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VLSI Chip Power Density
Source Intel?
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Specific Topics on Low-Power

• Power dissipation in CMOS circuits
• Device technology
• Low-power CMOS technologies
• Energy recovery methods
• Circuit and gate level methods
• Logic synthesis
• Dynamic power reduction techniques
• Leakage power reduction
• System level methods
• Microprocessors
• Arithmetic circuits
• Low power memory technology
• Test Power
• Power estimation

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Power in a CMOS Gate
VDD
iDD(t)
Ground
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Power Dissipation in CMOS Logic (0.25µ)
Ptotal (0?1) CL VDD2 tscVDD Ipeak
VDDIleakage
CL
75
5
20
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Power and Energy

• Instantaneous power (Watts)
• P(t) iDD(t) VDD
• Peak power (Watts)
• Ppeak Max P(t)
• Average power (Watts)
• Pav ?0T P(t) dt /T
• Energy (Joules)
• E ?0T P(t) dt

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Components of Power

• Dynamic
• Signal transitions
• Logic activity
• Glitches
• Short-circuit
• Static
• Leakage

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Power of a Transition
Power CVDD2/2
R
C
R
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Logic Activity and Glitches
1
6
2
5
4
3
d1
d1
d2
7
d1
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Low-Power Design Techniques

• Circuit and gate level methods
• Reduced supply voltage
• Adiabatic switching and charge recovery
• Logic design for reduced activity
• Reduced Glitches
• Transistor sizing
• Pass-transistor logic
• Pseudo-nMOS logic
• Multi-threshold gates

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Low-Power Design Techniques

• Functional and architectural methods
• Clock suppression
• Clock frequency reduction
• Supply voltage reduction
• Power down
• Algorithmic and Software methods

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Test Power

• Power grid on a VLSI chip is designed for certain
  current capacity during functional operation
• Average current ? heat dissipation
• Peak current ? noise, ground bounce
• Problem Tests like scan or BIST are
  nonfunctional and may cause higher than the
  functional circuit activity a functionally good
  chip can fail the test.

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Power Estimation Methods

• Spice Accurate but expensive
• Logic-level
• Event-driven simulation
• Statistical
• Probabilistic
• High-level Hierarchical

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Student Evaluation

• Homework (30) almost 1/week
• Class Project (30)
• Student presentation (10)
• Final Exam (30)