EET 3350 Digital Systems Design

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EET 3350Digital Systems Design
VHDL Additional Details Examples

• Dan Solarek

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VHDL Modeling Styles

• Dataflow
• Most are like assigning expressions to signals
• Structural
• Define explicit components and the connections
  between them.
• Behavioral
• Write an algorithm that describes the circuits
  output

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VHDL Dataflow Style

• Dataflow description
• The detail is less when compared with the
  structural description
• Concurrent statements include assignment and
  select statements
• Concurrency is needed to model the behavior of
  parallel, interconnected hardware elements
• Data dependencies are described, not the
  components and connections
• Includes when-else and with-select statements

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VHDL Structural Style

• A structural description is just like the
  schematic
• Includes concurrent statements
• A component statement is a concurrent statement
• All interconnections are precisely described

2-to4 DCD V2to4dec
Y0
I0
Y1
I1
Y2
EN
Y3
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VHDL Behavioral Style

• Behavioral description
• May not be synthesizable or may lead to a very
  large circuit
• Primarily used for simulation
• Normally uses VHDL processes
• Each VHDL process executes in parallel with other
  VHDL processes and concurrent statements
• But sequential statements can be used within a
  process

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What is a PROCESS?

• A process is a sequence of instructions, referred
  to as sequential statements.

the keyword process

• A process can be given a unique name using an
  optional LABEL
• This is followed by the keyword process
• The keyword BEGIN is used to indicate the start
  of the process
• All statements within the process are executed
  SEQUENTIALLY. Hence, order of statements is
  important.
• A process must end with the keywords end process.

TESTING process begin TEST_VECTORlt00 wai
t for 10 ns TEST_VECTORlt01 wait for 10
ns TEST_VECTORlt10 wait for 10
ns TEST_VECTORlt11 wait for 10 ns end
process
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Process Sensitivity List

• List of signals to which the process is
  sensitive.
• Whenever there is an event on any of the signals
  in the sensitivity list, the process starts.
• Every time the process starts, it will run in its
  entirety.
• WAIT statements not allowed in a processes with a
  sensitivity list.

• label process(sensitivity list)
• declaration part
• begin
• statement part
• end process

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VHDL Processes

• Processes Describe Sequential Behavior
• Processes in VHDL Are Very Powerful Statements
• Allow you to define an arbitrary behavior that
  may be difficult to represent by a real circuit
• Not every process can be synthesized
• Use Processes with Caution in the Code to Be
  Synthesized
• Use Processes Freely in Testbenches

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VHDL Design Styles
VHDL Design Styles
structural
behavioral
Components and interconnects
Concurrent statements
Sequential statements

• Registers
• State machines
• Test benches

Subset most suitable for synthesis
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VHDL Details Design Flow

• VHDL compiler analyzes code for syntax errors and
  checks for compatibility with other modules
• Synthesizer converts VHDL program to a circuit
  with components
• Place and route fits the circuit to a device

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• Elements of VHDL

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Logic Operators

• VHDL provides the following predefined basic
  logic operators

Keyword and or xor xnor nand nor not
Definition conjunction inclusive or exclusive
or complement exclusive or complement
conjunction complement inclusive or complement
only predefined in VHDL-93
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Logic Operators (cont.)

• Predefined operators are all binary except for
  not
• Multi-input operators formed from series of
  binary operators
• NAND-3 A nand B nand C
• Expression evaluation differs from switching
  algebra
• and, or, nand, nor are short-circuit operators
• right operand not evaluated if left operand
  determines result

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Operator Precedence

• Unary not has a higher precedence than any
  binary operator
• ALL binary operators have the SAME precedence
• Operators with the same precedence are evaluated
  left-to-right
• Operators in parentheses are evaluated first
  innermost to outermost order
• Must be used for proper AND - OR evaluation

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Concurrency

• Software source code statements execute in
  page/line order (i.e., sequential order)
• VHDL concurrent signal assignments execute only
  when associated signal change value (i.e.,
  concurrent order)
• page/line sequence has nothing to do with
  execution
• assignments are on a nonprocedural stimulus/
  response basis (event driven)
• signal assignments may trigger other concurrent
  assignments

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Concurrent Operation Example
entity XOR2_OP is port (A, B in
std_logic Z out std_logic) end
XOR2_OP architecture AND_OR_CONC of XOR2_OP is
signal INT1, INT2 std_logic begin Z
lt INT1 or INT2 INT2 lt not A and B
INT1 lt A and not B end AND_OR_CONC
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Design Units and Libraries

• VHDL is defined such that more complex pieces are
  built from simpler pieces

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Design Units and Libraries (cont.)

• Part of a VHDL model that can be independently
  analyzed (error checked) is a design unit
• Primary Design Units
• Entity Declaration
• Package Declaration
• Configuration Declaration
• Secondary Design Units
• Architectural Body
• Package Body
• Primary units analyzed before secondary units

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Design Units and Libraries (cont.)

• Two predefined libraries in VHDL
• STD - contains predefined VHDL constructs such as
  types, objects, etc.
• WORK - the working library
• Many other libraries may exist as part of
  development environment
• IEEE library - standard types and operators
  needed for simulation and implementation
• User-defined libraries - designs for reuse
• Implementation specific libraries - logic families

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• VHDL in Brief

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VHDL features

• Designs can be decomposed hierarchically
• Each design element has
• A well-defined interface for connecting with
  other elements
• Precise functional description (for simulation)
• Functional description may be
• Behavioral algorithm (direct functional
  description)
• Hardware structural description (such as in terms
  of gates and their interconnections)

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VHDL features (contd)

• Concurrency, timing, and clocking can all modeled
  in great detail (and complication!)
• complex timing models scare many people away from
  VHDL.
• But to know enough VHDL to describe a circuit is
  really not so bad.
• The logical operation and timing behavior of a
  design can be simulated

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VHDL Program Structure

• VHDL was designed with structured programming in
  mind
• Borrowed concepts from Pascal and ADA
• Actually VHDL is almost object-oriented
• Has separate interface and implementation parts!
• But, doesnt have classes with which to
  instantiate new objects with.

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VHDL Structure Entity and Architecture

• Entity simply a declaration of a modules inputs
  and outputs.
• Like an interface
• Like a wrapper and a hook
• Architecture a detailed description of whats
  inside a module. Like an implementation.
• You need both parts.
• You can have multiple implementations for each
  interface, but must statically bind some unique
  implementation with each interface

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A simple example
entity Inhibit is -- a.k.a. but-not as in X
but not Y port (X,Y in BIT Z
out BIT end Inhibit -- end of entity
declaration architecture Inhibit_arch of Inhibit
is begin Z lt 1 when X1 and Y0 else
0 end Inhibit_arch -- end of architecture
declaration
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Syntax of VHDL entity
entity entity-name is port (signal-names
mode signal-type signal-names mode
signal-type signal-names mode
signal-type) --careful here! end entity-name
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Some explanation

• Signal-names comma-separated list of 1 or more
  user-selected identifiers to name
  external-interface signals
• Mode signal direction
• in, out, buffer (output which is also readable
  inside entitys architecture), inout (often used
  for 3-state i/o pins)
• Signal-type built-in or user-defined signal
  type. Later.

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SyntaxVHDL architecture
architecture arch-name of entity-name is type
declarations signal declarations constant
declarations function definitions procedure
definitions component declarations begin
concurrent-statements end arch-name
named wires
later
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types

• A type is the set of values
• Every signal, variable, and constant in VHDL has
  a type
• To each type theres typically also an associated
  set of operators (add, AND, etc.).
• VHDL has just a few predefined types.
• The only ones well see here are integer,
  character, and boolean
• There are also built-in types bit and bit_vector,
  but the user-defined types std_logic and
  std_logic_vector are more useful (IEEE 1164 std)
• Subtyping is allowed (only subranges, please!)
• Theres more stuff in book (pp 262-263)

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Array types
General syntax of array typedef

• type type-name is array (start todownto end) of
  element-type
• type type-name is array (range-type) of
  element-type etc.

Examples of array typedef
type byte is array (7 downto 0) of
STD_LOGIC constant WORD_LEN integer 32 type
word is array (WORD_LEN-1 downto 0 of STD_LOGIC
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Accessing array elements

• Use array name and the index in parentheses
• M(11), W(WORD_LEN-5), R(1,0)
• A 2-d array is just an array of 1-d arrays
• Can also specify values by index, like this
• W (0gt0, 8gt0, 16gt0, 24gt0,
• othersgt1)

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Another way of writing array literals of a
STD_LOGIC array
Use a string as follows W
11111110111111101111111011111110 -- same
result as previous example!
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The most important array type in typical VHDL
programs!

• Thats the IEEE 1164 std user-defined logic type
  std-logic-vector
• This defines an ordered set of std_logic bits
• Heres the def of the type

type STD_LOGIC_VECTOR is array (natural range lt
gt) of STD_LOGIC

• an example of an unconstrained array type
• The range of the array is unspecificed, except
  that it must be a subrange of a defined type, in
  this case, natural (0, 1, 2,).
• Actual range is specified when a signal or
  variable is assigned this type

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functions

• See syntax in Table 5-22, p. 266
• Example, Table 5-23, p. 266 but-not gate using a
  function.
• See next slide

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But-not gate using a function
architecture Inhibit_archf of Inhibit is function
ButNot (A,B bit) return bit is begin if B
0 then return A else return 0 end
if end ButNot begin Z lt ButNot(X,Y) end
Inhibit_archf
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Libraries and packages

• LIBRARY a place where VHDL compiler stores
  information about a particular design project
• Intermediate files used in the analysis,
  simulation, synthesis of design
• Library location is implementation-dependent
• For each design, the compiler automatically
  creates and uses a library named work
• When compiler analyzes each file in the design,
  it puts the results there.
• Other libraries may also be used.
• Common libraries shared by various designs
• Standard libraries such as ieee, Xilinxs unisim

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Library statement in VHDL

• library ieee
• -- needed if you want to use the ieee library
• library unisim
• -- will see this in Xilinx-generated files
• library work
• -- implicitly included in every VHDL file

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packages

• Specifying a library name in a design gives it
  access to any previously analyzed entities and
  architectures stored in the library
• But it doesnt give access to type definitions
  and the like
• This is what packages and use clauses are for

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Whats in a package?

• A package is a file containing definitions of
  objects that can be used in other programs
• Is an ADA concept
• Like the entity-architecture pair, the package is
  another precursor to the OOP idea!
• object here means signals, types, constants,
  functions, procedures, components declarations,
  etc. NOT objects as in OOP.

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Using a package

• The things in a pkg are global
• Available to any VHDL entity that uses the
  package
• Types and constants defined in a pkg are known in
  any file that uses the pkg
• Functions and procedures defined in a pkg can be
  called in files that use the pkg
• To use a package you say use for example
• use ieee.std_logic_1164.all -- use all
  definitions in pkg
• use ieee.std_logic_1164.std_ulogic -- use just
  def std_ulogic type

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Structural design elements

• Finally ready to look at the guts of a VHDL
  design, the executable part of the code!
• Recall that the body of an architecture is a
  series of concurrent statements
• Each one of these execute simultaneously with the
  other ones in the same architecture body
• Quite different from a typical software
  program!!!
• If the last stmt updates a signal thats used by
  the first stmt (as input), then the simulator
  will go back to the first stmt and update its
  results accordingly!!

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Concurrent statements in VHDL

• VHDL has different kinds of concurrent statements
• Component statements
• Concurrent signal assignment statements
• Process statements
• Also has ways of bundling a set of sequential
  statements to operate as a single concurrent
  statement
• These statements give rise to 3 somewhat distinct
  styles of circuit design and description!

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Component statements