EET 3350 Digital Systems Design Textbook: John Wakerly Chapter 8: 8.78.9

1
EET 3350 Digital Systems Design Textbook John
Wakerly Chapter 8 8.78.9

• Synchronous Design Methodology
• Asynchronous Inputs
• Synchronizers and Metastability

2
Practical Design Considerations

• Divide and Conquer
• Smaller blocks
• Avoiding FSMs that are too complex
• Control Unit and Data Path
• Clock skew
• Clock gating
• Asynchronous inputs
• Synchronizers
• Synchronizer failure
• Metastability

3
Synchronous System Structure

• Overview, Block Diagram, Design Goals, Multiplier
  Example

4
Synchronous System Structure

• Usually, synchronous digital systems can be
  partitioned into two major subsystems
• More manageable number of states
• FSM design possible

5
Synchronous System Structure

• Everything is clocked by the same, common clock

6
Synchronous System Design Goals

• Minimize clock skew
• Calculate the magnitude of what cannot be
  eliminated
• Ensure that Flip-Flops have sufficient setup-time
  and hold-time margins
• Insurance against clock skew
• Synchronize any asynchronous inputs
• Synchronize with the clock
• Assure low probability of synchronizer failure

7
Typical Synchronous-System Timing

• Outputs have one complete clock period to
  propagate to inputs
• Must take into account flip-flop setup times at
  next clock period

8
Example Shift-and-Add Multiplier

• Realize the multiplier as a synchronous system.

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Example Shift-and-Add Multiplier

• Sums each partial product, one at a time
• Each partial product is shifted versions of A or
  0

Control Algorithm 1. P ? 0, A ? multiplicand,
B ? multiplier 2. If LSB of B1 then add A
to P else add 0 3. Shift PB right 1
4. Repeat steps 2 and 3 n-1 times. 5. PB has
product.
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Example Shift-and-Add Multiplier

• Components used to implement this example
  multiplier

SN 74 LS 04 SN 74 LS 08 SN 74 LS 157 SN 74 LS
163 SN 74 LS 194 SN 74 LS 283 SN 74 LS 377
Hex Inverter Quad 2-input AND Quad 2-to-1
Mux/DS 4-Bit Binary Counter 4-Bit Bidirectional
Universal Shift Register 4-Bit Binary Adder 8-Bit
D Flip-Flop Register
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Multiplier Data Paths
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Multiplier Control Unit
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Control-Unit State Machine
Note Control outputs are 0 unless otherwise
indicated.
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Example Shift-and-Add Multiplier

• The primary purpose of this example is to
  illustrate a complete, realistic synchronous
  system
• Take the time to carefully review the example as
  it includes several important aspects
• Implementation of an algorithm in hardware
• Use of common MSI components as building blocks
• Division of the system into data path and control
  units
• and more

15
Impediments to Synchronous Design

• Clock Skew, Gating the Clock, Asynchronous Inputs

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Clock Skew

• Clock signal may not reach all flip-flops
  simultaneously
• Output changes of flip-flops receiving early
  clock may reach D inputs of flip-flops with
  late clock too soon

Reasons for slowness(a) wiring delays (b)
capacitance (c) incorrect design
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Clock-Skew Calculation

• tffpd(min) tcomb(min) - thold - tskew(max) 0
• First two terms are minimum time after clock edge
  that a D input changes
• Hold time is earliest time that the input may
  change
• Clock skew subtracts from the available
  hold-time margin
• Compensating for clock skew
• Longer flip-flop propagation delay
• Explicit combinational delays
• Shorter (even negative) flip-flop hold times

18
Clock Distribution

• In a large system, a single clock generator may
  not have a large enough fanout
• To address this, we can buffer the clock signal
• First, an example of bad clock distribution

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Automatic Clock Distribution

• This is what a typical ASIC/FPGA router will do
  if you dont lay out the clock by hand

20
Clock Distribution in ASICs

• Propagation delays due to different lengths,
  different conductors
• Variability can cascade, multiply problems

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Clock-Tree Solution

• Often laid out by hand in the CAD tool
• Wide, fast metal (low R, fast RC time constant)

22
Gating the Clock

• Avoid gating the clock signal
• Glitches possible if the control signal (CLKEN)
  is generated by the same clock
• Excessive clock skew in any case

23
A Better Approach

• If you really must gate the clock...
• use the gating at right
• all clock signals are synchronized as they suffer
  the same delay

24
Asynchronous Inputs

• Not all inputs are synchronized with the clock
• Examples
• Keystrokes
• Sensor inputs
• Data received from a network (transmitter has its
  own clock)
• Inputs must be synchronized with the system
  clock before being applied to a synchronous
  system.

Note Asynchronous inputs change infrequently
when compared to the synchronous systems
internal activity
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A Simple Synchronizer

• The probability that a flip-flop stays in the
  metastable state decreases exponentially with
  time
• Therefore, any scheme that delays using the
  signal can be used to decrease the probability of
  failure
• In practice, delaying the signal by a cycle is
  usually sufficient

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A Simple Synchronizer

• For a single asynchronous input, we use a simple
  Flip-Flop to bring the external input signal into
  the timing domain of the system clock

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A Simple Synchronizer

• The D flip-flop samples the asynchronous input at
  each cycle and produces a synchronous output that
  meets the setup time of the next stage.

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Only One Synchronizer Per Input

• It is essential for asynchronous inputs to be
  synchronized at only one place

what NOT to do
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Only One Synchronizer Per Input

• Two flip-flops may not receive the clock and
  input signals at precisely the same time (clock
  and data skew)
• When the asynchronous changes near the clock
  edge, one flip-flop may sample input as 1 and the
  other as 0

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A Bigger Problem

• Combinational delays to the two synchronizers are
  likely to be different

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The Best Solution

• Single point of synchronization is even more
  important when input goes to a combinational
  logic block
• The CL block can accidentally hide the fact that
  the signal is synchronized at multiple points
• The CL magnifies the chance of the multiple
  points of synchronization seeing different values

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Synchronizer Failure and Metastability

• Synchronizer Failure, Metastability Resolution
  Time, Reliable Synchronizer Design, Analysis of
  Metastable Timing

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Recommended Synchronizer Design

• Hope that FF1 settles down before META is
  sampled
• In this case, SYNCIN is valid for almost a full
  clock period
• Can calculate the probability of synchronizer
  failure (FF1 still metastable when META sampled)

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Metastability Decision Window

• Timing parameters for metastability analysis
• Normal Flip-Flop operation

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Metastability Resolution Time

• Timing parameters for metastability analysis
• Metastable behavior

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Flip-Flop Metastable Behavior

• We think of flip-flops having only two stable
  states - but all have a third metastable state
  halfway between 0 and 1.
• When the setup and hold times of a flip-flop are
  not met, the flip-flop could be put into the
  metastable state.
• Noise will be amplified and push the flip-flop
  one way or other.
• However, in theory, the time to transition to a
  legal state is unbounded.
• Does this really happen?
• The probability is low, but the number of trials
  is high!

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Flip-Flop Metastable Behavior

• Probability of Flip-Flop output being in the
  metastable state is an exponentially decreasing
  function of tr (time since clock edge, a.k.a.
  resolution time)
• Stated another wayMTBF(tr) exp(tr /t) / T0 f
  a , wheret and T0 are parameters for a
  particular Flip-Flop,f is the clock frequency,
  and a is the number of asynchronous transitions
  per second

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MTBF

• Mean Time Between Failure
• the average time between failures for a given
  piece of equipment or equipment set
• an aid in predicting the reliability of
  electronic equipment under different operating
  conditions
• not a guarantee of useable product lifetime, but
  is a guide for planning the operational use of
  the equipment

74LS74 _at_ 100KHz ? 3.6 x 1011 sec 115 centuries
74LS74 _at_ 16MHz ? 3.1 sec
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Flip-Flop Metastability Parameters

• Parameters for several common logic families

MTBF
as t ? MTBF ? as f ? MTBF ?
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Realistic Values for MTBF

• If MTBF 1000 years and you ship 52,000 copies
  of the product, then some system experiences a
  mysterious failure every week
• Real-world MTBFs must be much higher
• How to get better MTBFs?
• Use faster flip-flops (reduce value of t)
• But clock speeds keep getting faster, thwarting
  this approach
• Wait for multiple clock ticks to get a longer
  metastabilty resolution time (increase value of
  t)
• Waiting longer usually doesnt hurt performance
• unless there is a critical round-trip handshake

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Multiple-Cycle Synchronizer

• Clock-skew problem

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Deskewed Multiple-Cycle Synchronizer

• Necessary in really high-speed systems
• DSYNCIN is valid for almost an entire clock
  period.

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Cascaded Synchronizer

• Just a shift register
• Used for higher frequencies
• Attempt to avoid clock-skew limitations
• Overall probability of failure is on the order of
  the nth power of one Flip-Flop at same f

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Cascaded Synchronizer

• This approach is based on the assumption that one
  of the Flip-Flops will (eventually) resolve the
  metastability
• In a PLD, this is easy to implement as there are
  Flip-Flops available external ones are not
  needed

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High-Speed Data Transfers

• A common situation is the difference between the
  PC system clock and the NRZ serial data received
  via an Ethernet link

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High-Speed Data Transfers

• Ethernet synchronizer

digital phase locked loop
?
NRZ serial data
looking for pattern in data (frame)
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High-Speed Data Transfers

• Ethernet link and system clock timing

100 MHz
33.33 MHz
SYNC pulse after every frame
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High-Speed Data Transfers

• Ethernet byte holding register and control
• Used with Ethernet synchronizer to provide more
  time to detect and process received data

?
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High-Speed Data Transfers

• Timing for SBYTE and possible timing for SLOAD

increase from 10ns to 80ns processing time
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High-Speed Data Transfers

• SCTRL circuit for generating SLOAD

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High-Speed Data Transfers

• Timing for the SCTRL circuit

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High-Speed Data Transfers

• Maximum-delay timing for SCTRL circuit

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High-Speed Data Transfers

• Half-clock-period SCTRL circuit for generating
  SLOAD

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High-Speed Data Transfers

• Synchronous timing with slow (10-MHz) RCLK

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High-Speed Data Transfers

• Synchronizer with edge-triggered SYNC detection

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Assignments

• Continue work on project
• Read over the web page on state reduction
• Read chapter 9