Relationship between Address Width and Memory Height - PowerPoint PPT Presentation

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Title:

Relationship between Address Width and Memory Height

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... (C/S) pins on the memory pack to complete the addressing. Sometimes the address is not fully decoded What happens then? – PowerPoint PPT presentation

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Title: Relationship between Address Width and Memory Height


1
Relationship between Address Width and Memory
Height
1111 1111 1111 1111 11111 1111


16 MB



Memory height 224
0000 0000 0000 0000 0000 0000
Address Width 24
Memory Width
2
When CPU sends out an address 0010 0001 1111
1010
Upper part The memory Chip
Lower part The memory cell within the Chip
Extra Decoder Logic is needed to select the
correct Memory Chip. If this is not done, all the
Chips will respond to the every CPU
call. Example phone area code.
If 2 Chips respond simultaneously ---gt System
crash!
3
Memory Map for a small computer system
Device Size Pins 32 address bus Address Range
PROM1 RAM 1 RAM 2 RAM 3 1 Mbyte 16 Mbyte 16 Mbyte 16 Mbyte 20 24 24 24 0000 0000 xxxx 0000 0001 0000 0010 0000 0011 0000 0000 000F FFFFF 0100 0000 01FF FFFF 0200 0000 02FF FFFF 0300 0000 03FF FFFF
Designing computer memories to deliver the best
possible access Times for users an maximum
flexibility for administrators, when they
Install extra modules, is complex and tricky
4
Usually memory RAMs and ROMs are not normally
matched to the width of the address buss. What
happens then? The remaining address buses will
be fed to into a separate decoder that will
connect to the Chip select (C/S) pins on the
memory pack to complete the addressing.
5
Sometimes the address is not fully decoded What
happens then? Multiple images of memory packs
within the same address. ( it is not a huge deal,
it can still work )
6
Some computers have their IO ports inserted into
the main memory map. --gt This will cause an
inconvenient segmentation of the memory. And
Decoding circuits will be a way more conplex
because of the routine differences in access
times between memory and port chips








IO Dev 1
CPU
80 0000- 80 002F
IO Dev 2
Lots of Unused space
RAM 2
RAM 1
ROM
00 0000- 01 FFFF
Memory Map
7
IO Mapped scheme is the scheme where IO have
different region in the address than the memory
chips. Space occupied between the 2 is largely
different 4G compared to 64k To provide this
scheme, the CPU needs to provide special
instructions e.g. IN and OUT and more bus
signals are needed.
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