Systems Engineering Project: System Validation and Verification Using SDL

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Systems Engineering ProjectSystem Validation
and VerificationUsing SDL
Ron Henry ENSE 623 November 30, 2004
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Formalisms for Automated VV

• Several standard notations have evolved in
  support of automated validation and verification
• Specification and Description Language (SDL)
• Message Sequence Charts (MSC)
• Test and Test Control Notation (TTCN)
• These formalisms are considered complementary
• MSCs (familiar from UML sequence diagrams) are
  used both to specify requirements and to trace
  execution
• SDL is used to specify the system architecture
  and state-machine model
• TTCN is an abstract representation for test cases

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Characteristics of SDL

• Major language features
• Formal, hierarchical data flow diagrams
• Extended finite state machines (EFSMs)
• Local variables
• Timers
• SDL Evolution
• Widely used in telecommunications industry
• First ITU Z.100 recommendation in 1980
• Updated every ?4 years
• SDL-92 added support for object-oriented features
• SDL-2000 adds support for hierarchical EFSMs
  (equivalent to Statecharts)

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Commercial Tools for SDL-Based VV

• Tools can provide a variety of functions
• Graphical editing syntax checking
• Model checking (static analysis)
• Executable simulation animation of a model
• Validation of a model against a use case
• Specification-based generation of test cases
• Telelogic appears to be market leader in this
  area
• Tau/SDL is one of the leading tools
• ObjectGeode also acquired by Telelogic
• SAFIRE-SDL by Solinet
• Tau/SDL was used for this project
• 15 licenses available under arrangement with UMD
  (handled through Prof. Basili in CS dept.)
• C compiler (Borland recommended) must be
  installed in order to generate executables for
  simulation and validation

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General Methodology
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Remote Observing Platform System Context
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Remote Observing Platform Domain Model
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MSC TurnOnInstrument
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MSC TurnOffInstrument
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MSC Observe
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Tau/SDL Model Structure
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Observatory System Diagram
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InstrumentModule Block Diagram
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CAM1 Block Diagram
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Shutter Process Diagram
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CameraManager Process Diagram
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Inheritance in SDL HomingCameraManager
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Tau/SDL Simulator User Interface
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MSC Observe Process-Level Simulator Trace
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Tau/SDL Validator User Interface
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Tau/SDL Validator Report Summary
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Tau/SDL Validator Trace Implicit Signal
Consumption
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Model Validation MSC TurnOnInstrument
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Model Validation MSC Observe
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MSC-Based Testing TTCN Structure
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Test Case Generated from Observe MSC
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VV with SDL Project Summary

• This project has demonstrated a robust framework
  for VV based on SDL
• Hierarchical data flow diagrams are well suited
  to formalizing complex system architectures
• VV is accomplished through following steps
• 1. Basic usability testing and sanity checking is
  done manually using a simulator
• 2. SDL model is automatically validated against
  use cases in the form of MSCs
• 3. MSCs are then used to generate TTCN test cases
• Tau/SDL is a powerful tool, but its complexity
  presented challenges
• Not all features worked
• Generated executables subject to unexplained
  crashes
• Error messages not always clear