Arithmetic for Computers

1
Arithmetic for Computers
2
Numbers

• Bits are just bits (no inherent meaning)
• Conventions define relationship between bits and
  numbers
• Binary numbers (base 2) 0000 0001 0010 0011 0100
  0101 0110 0111 1000 1001... decimal 0...2n-1
• Of course it gets more complicated
• Numbers are finite (overflow)
• Fractions and real numbers
• Negative numberse.g., no MIPS subi instruction
  addi can add a negative number
• How do we represent negative numbers?
• i.e., which bit patterns will represent which
  numbers?

3
Possible Representations

• Sign Magnitude One's
  Complement Two's Complement 000
  0 000 0 000 0 001 1 001 1 001
  1 010 2 010 2 010 2 011 3 011
  3 011 3 100 -0 100 -3 100 -4 101
  -1 101 -2 101 -3 110 -2 110 -1 110
  -2 111 -3 111 -0 111 -1
• Issues balance, number of zeros, ease of
  operations
• Which one is best? Why?

4
Binary Numbers

• 32 bit signed numbers0000 0000 0000 0000 0000
  0000 0000 0000two 0ten0000 0000 0000 0000 0000
  0000 0000 0001two 1ten0000 0000 0000 0000
  0000 0000 0000 0010two 2ten
• ...
• 0111 1111 1111 1111 1111 1111 1111 1110two
  2,147,483,646ten0111 1111 1111 1111 1111 1111
  1111 1111two 2,147,483,647ten1000 0000 0000
  0000 0000 0000 0000 0000two
  2,147,483,648ten1000 0000 0000 0000 0000 0000
  0000 0001two 2,147,483,647ten1000 0000 0000
  0000 0000 0000 0000 0010two 2,147,483,646ten
• ...
• 1111 1111 1111 1111 1111 1111 1111 1101two
  3ten1111 1111 1111 1111 1111 1111 1111 1110two
  2ten1111 1111 1111 1111 1111 1111 1111 1111two
  1ten

5
Byte Ordering

• How should bytes within multi-byte word be
  ordered in memory?
• Conventions
• Suns, Macs are Big Endian machines
• Least significant byte has highest address
• Alphas, PCs are Little Endian machines
• Least significant byte has lowest address
• Example
• x 0x01234567, address of x 0x100

Big Endian
Little Endian
6
Two's Complement Operations

• Negating a two's complement number
• Invert all bits and add 1 (e.g., 1s complement
  1)
• Remember negate and invert are quite
  different!
• Convert n bit numbers into numbers with more than
  n bits
• MIPS 16 bit immediate gets converted to 32 bits
  for arithmetic
• Copy the most significant bit (the sign bit) into
  the other bits 0010 -gt 0000 0010 1010 -gt
  1111 1010
• Sign extension
• Load byte (signed vs. unsigned) assume
  Memorya0 123456FF16
• lb s0, (a0) s0 FFFFFFFF16 ( -110)
• lbu s0, (a0) s0 000000FF16 ( 25510)

7
Addition Subtraction

• Just like in elementary school (carry/borrow
  1s) 0111 0111 0110  0110 - 0110 - 0
  101
• Two's complement operations easy
• Subtraction using addition of negative numbers
  0111 0111  1010 24 - 0110
• Overflow (result is too large for finite
  computer word)
• e.g., adding two n-bit numbers does not yield an
  n-bit number 0111  0001 Note that overflow
  term is somewhat misleading, 1000 it does not
  mean a carry overflowed

8
Detecting Overflow

• No overflow
• When adding a positive and a negative number
• When signs are the same for subtraction
• Overflow occurs when the value affects the sign
• When adding two positives yields a negative
• When adding two negatives gives a positive
• When subtract a negative from a positive and get
  a negative
• When subtract a positive from a negative and get
  a positive
• Consider the operations A B, and A B
• Can overflow occur if B is 0 ?
• Can overflow occur if A is 0 ?

9
Effects of Overflow

• An exception (interrupt) occurs
• Control jumps to predefined address for exception
• Interrupted address is saved for possible
  resumption
• Details based on software system / language
• Example flight control vs. homework assignment
• Don't always want to detect overflow
• New MIPS instructions addu, addiu, subu note
  addiu still sign-extends! note sltu,
  sltiu for unsigned comparisons

10
Multiplication

• More complicated than addition
• Accomplished via shifting and addition
• More time and more area
• Let's look at 3 versions based on elementary
  school algorithm 0010
  (multiplicand) X 1011 (multiplier)
  0010
• 0010
• 0000
• 0010
• 0010110
• Negative numbers
• Convert to positives and multiply decide sign
• There are better techniques (e.g., Booths
  algorithm), but we will skip

assume unsinged
11
Multiplication 1st Implementation
Datapath
Control
12
Refined Version

• Save register space and use 32-bit ALU
• 32 bit multiplicand register
• No extra multiplier register
• Multiplier starts in right half of product
• With zeros in the left half of product

13
Fast Multiplication - Parallel Version

• Many transistors are available
• 31 adders for multiplication of 32 bit numbers
• Upper 31 bits carry bit to the next level,
• 1 bit LSB to the product of final result
• Pipelining for many multiplications
• Can process multiple multiplications in pipeline

14
Division

• Basically subtract and shift one bit by one bit
• Same algorithm from elementary school
• 1001
• 1000 )1001010
• -1000
• 10
• 101
• 1010
• -1000
• 10
• 3 versions for division similar to multiplication
• 64-bit ALU version
• 32-bit ALU version
• Faster division (no parallel version, but SRT
  division)

(quotient)
(divisor)
(dividend)
(remainder)
15
Floating Point (a brief look)

• We need a way to represent
• Numbers with fractions, e.g., 3.1416
• Very small numbers, e.g., 0.000000001
• Very large numbers, e.g., 3.15576 x 109
• Representation
• Sign, exponent, significand (1)sign x
  significand x 2exponent
• More bits for significand gives more accuracy
• More bits for exponent increases range
• IEEE 754 floating point standard
• Single precision 8 bit exponent, 23 bit
  significand, 1 bit sign
• Double precision 11 bit exponent, 52 bit
  significand, 1 bit sign

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Fractional Binary Numbers
2i
2i1
4

2
1
1/2

1/4
1/8
2j

• Representation
• Bits to right of binary point represent
  fractional powers of 2
• Represents rational number

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Fractional Binary Numbers (contd)

• Examples
• Value Representation
• 5 3/4 101.112
• 2 7/8 10.1112
• 0.1111112 represents just below 1.0
• 1/2 1/4 1/8 1/2i ? 1.0 (notation
  1.0 ?)
• Representable Numbers
• Can only exactly represent numbers of the form
  x/2k
• Other numbers have repeating bit representations
• Value Representation
• 1/3 0.0101010101012
• 1/5 0.00110011001100112
• 1/10 0.000110011001100112

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IEEE 754 FP Normalized Values

• Condition exponent ? 0000 and exponent ? 1111
• Significand coded with implied leading 1
• significand 1.xxxx2
• Minimum when 0000 (significand 1.0)
• Maximum when 1111 (significand 2.0 - ?)
• Get extra leading bit for free
• Exponent is biased to make sorting easier
• exponent 1 254
• bias 127 for single precision (1023 for double
  precision)
• format (1)sign x (1 significand) x
  2exponent bias

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IEEE 754 FP Normalized Values (contd)

• Example for -0.75
• Decimal -.75 - ( ½ ¼ )
• Binary -.11 -1.1 x 2-1
• Floating point exponent 126 01111110
  (-1126-127)
• IEEE single precision
• -0.75 (-1)1 x (1 .100000000000) x 2 126-127
• Another example for 15213.0
• 1521310 111011011011012 1.11011011011012 x
  213
• significand 1101101101101 (implied leading
  1)
• exponent 140 100011002 (exponent bias
  13, bias 127)

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IEEE 754 FP Denormalized Values

• Condition exp 0000
• Value
• exponent 1 bias (e.g. single precision -126
  1-127)
• significand 0.xxxx2 (no implied leading 1)
• Cases
• exp 0000, frac 0000
• Represents value 0
• Note that have distinct values 0 and -0
  (depending on sign bit)
• exp 0000, frac ? 0000
• Numbers very close to 0.0 (-1 x 2-126, 1 x
  2-126)
• Gradual underflow possible numeric values are
  spaced evenly near 0.0

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IEEE 754 FP Special Values

• Condition exp 1111
• exp 1111, frac 0000
• Represents value ? (infinity)
• Operation that overflows
• Both positive and negative
• e.g. , 1.0/0.0 -1.0/-0.0 ?,
• 1.0/-0.0 -?
• exp 1111, frac ? 0000
• Not-a-Number (NaN)
• Represents case when no numeric value can be
  determined
• e.g., 0.0/0.0, sqrt(-1), ? - ?

22
IEEE 754 FP Summary
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Floating Point Addition

• Sketch of FP addition
• Align numbers to have the same exponent (the
  larger exponent)
• Add two significands with their signs and implied
  leading 1s
• Normalize the result, checking overflow and
  underflow
• Example for 0.5 -0.4375
• FP format 0.5 1.000 x 2-1, -0.4375 -1.110
  x 2-2
• Align to the larger exponent -1.110
  x 2-2 -0.111 x 2-1
• Addition of significands 1000
  -0111 0001
• Result 0.001 x 2-1
• Normalize 1.000 x 2-4
• Checking overflow and underflow -126 -4
  127

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Floating Point Addition Implementation

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Floating-Point Multiplication

• Sketch of FP multiplication
• Add exponents without bias
• Multiply two significands
• Check for underflow and overflow
• Normalize the result
• Set the sign bit
• Example for (1.000 x 2-1) x (-1.110 x 2-2)
• Exponents -1 (-2) -3
• Significand 1.000 x 1.110 1.110000
• Check -126 -3 127
• Normalize 1.110 x 2-3
• Sign bit -1.110 x 2-3

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Floating Point Complexities

• Operations are somewhat more complicated
• In addition to overflow we can have underflow
• Accuracy can be a big problem
• IEEE 754 keeps two extra bits (guard and round)
• Keep extra bits during intermediate additions
• Four rounding modes
• Choose close to actual numbers
• Programmers pick the desired one
• Other complexities
• Implementing the standard can be tricky
• Not using the standard can be even worse
• See text for description of 80x86 and Pentium bug!

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Floating Point Instructions (MIPS)

• Single precision and double precision
  instructions
• Addition add.s, add.d
• Subtraction sub.s, sub.d
• Multiplication mul.s, mul.d
• Division div.s, div.d
• Comparison c.x.s, c.x.d (x can be eq, neq,
  lt, le, gt, ge)
• Other instructions
• Branch bc1t, bc1f
• Comparison sets cond, check if cond 1
• Memory access lwc1, swc1 (32 bit data to FP
  register)
• Floating point registers
• 32 single precision registers f0, f1, f31
• 16 double precision registers combining two FP
  registers

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Ariane 5

• Ariane 5 tragedy (June 4, 1996)
• Exploded 37 seconds after liftoff
• Satellites worth 500 million
• Why?
• Computed horizontal velocity as floating point
  number
• Converted to 16-bit integer
• Careful analysis of Ariane 4 trajectory proved
  16-bit is enough
• Reused a module from 10-year-old software
• Overflowed for Ariane 5
• No precise specification for the S/W

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Summary

• Computer arithmetic is constrained by limited
  precision
• Bit patterns have no inherent meaning
• But standards do exist for number representations
• Twos complement, IEEE 754 floating point
• Computer instructions determine meaning of the
  bit patterns
• Performance and accuracy are important
• So there are many complexities in real machines
• Algorithm choice is important
• May lead to hardware optimizations for both space
  and time
• (e.g., multiplication)