High Frequency Behavioral Modeling of Second-Order S? Modulators

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High Frequency Behavioral Modeling of
Second-Order S? Modulators

• By
• George Suárez Martínez

Submitted in partial fulfillment of the
requirements for the degree of MASTERS OF
SCIENCE in Electrical Engineering February 28,
2006
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Presentation Outline

• Motivation
• Objectives
• Second-order Multi-bit S? Modulator (S??)
• Non-idealities
• Jitter Noise
• Thermal Noise
• Capacitance mismatch
• Individual Level Averaging (ILA)
• Switched-capacitor (SC) integrator
• Results
• Conclusions

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Motivation

• S? modulators (S?Ms) form part of the core of
  many todays mixed-signal designs as cornerstone
  components of oversampled S? data converters
• S? converters have become a promising candidate
  for high-speed, high-resolution, and low-power
  mixed-signal interfaces
• Transistor-level simulation is the most accurate
  approach (e.g. SPICE)
• Impractical for complex systems, long simulation
  time can take more than a day for a single case!

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Motivation

• Alternate modeling techniques,
• Finite-difference equations (z-transform)
• Macromodels
• Look-up tables
• Behavioral models
• Accurate models are needed for low-power, high
  speed applications (e.g. GSM and WCDMA)
• VHDL for Analog and Mixed Signal (VHDL-AMS)
  becomes practical due to the mixed-signal nature
  of S? Modulators

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Objectives

• Develop an accurate behavioral model of a
  high-speed second-order multi-bit S??
• Make use and explore VHDL-AMS as the modeling
  language
• Develop modular and reusable models for other
  topologies of S??s
• Validate the model with SPICE simulations
• Validate the model with experimental data for
  target bandwidths of GSM (200kHz) and WCDMA (2.0
  MHz)

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Second-Order S?? (Ideal Model)
First Integrator
Second Integrator






0.5
1
-
-
5-level quantizer
0.5
1
DECODER DAC
0.5

• Lack of non-idealities
• Capacitance mismatch
• Jitter Noise
• Thermal Noise
• Integrator Dynamics
• Dynamic element matching behavior

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Second-Order S?? (Non-ideal Model)
Switched-Capacitor integrator dynamics
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Noise Sources - Jitter Noise

• Non-uniform sampling.
• For a sine wave the error can be approximated by,
• Assumed to be white, Gaussian noise

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Noise Sources - Thermal Noise

• Caused by the random motion of electrons due to
  thermal energy
• For switched-capacitor S??s thermal noise is due
  the integrator
• switches resistance
• operational transconductance amplifier (OTA)
• Based on track and hold operation of switched-
  capacitor (SC) systems

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Noise Sources - Thermal Noise
Sampling
Integration
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Capacitance Mismatch

• Integrator gains are built using capacitor ratios
• In multibit architectures DAC mismatch introduces
  harmonic distortion
• Dynamic Element Matching (DEM) such as Individual
  Level Averaging (ILA) is employed

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Individual Level Averaging (ILA)

• Internal DAC unitary model

DAC

• ILA algorithm transfer curves

ideal
Error due mismatch
ILA on
ideal
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Integrator Dynamics

• Limited DC gain
• Limited bandwidth
• Slew rate limitations
• Parasitic capacitances
• gm, go relationship
• Capacitive Loads

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Integrator transient behavior

• Possible scenarios in SC integrator transient
  response
• Linear va Io/gm
• Partial Slew va gt Io/gm and to t
• Slew va gt Io/gm and to lt t
• SR and to determine
• the scenario

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SC integrator transient equations
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Simulation Results - Model vs SPICE

• gm1.16 mA/V and T27oC.

Bandwidth SPICE SNDR Model SNDR Error ()
135kHz 86.56 dB 85.43 dB 1.31
270kHz 74.65 dB 70.35 dB 5.76
615kHz 54.99 dB 51.42 dB 6.50

• gm1.75 mA/V and T27oC.

Bandwidth SPICE SNDR New Model SNDR Error ()
135kHz 86.10 dB 84.63 dB 1.71
270kHz 72.45 dB 70.30 dB 2.96
615kHz 53.62 dB 51.34 dB 4.25
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Simulation Results - Model vs SPICE

• gm1.9 mA/V and T-30oC.

Bandwidth SPICE SNDR New Model SNDR Error ()
135kHz 89.90 dB 84.07 dB 6.48
270kHz 71.08 dB 71.04 dB 0.06
615kHz 53.53 dB 51.93 dB 2.99

• gm1. 9 mA/V and T27oC.

Bandwidth SPICE SNDR New Model SNDR Error ()
135kHz 87.57 dB 84.98 dB 2.95
270kHz 72.73 dB 70.54 dB 3.01
615kHz 53.37 dB 51.89 dB 2.78
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Simulation Results for GSM
VHDL-AMS 76.57 dB Actual data 74.50 dB
2.78 error
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Simulation Results for WCDMA
VHDL-AMS 76.57 dB Actual data 74.50 dB
2.41 error
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Results-Capacitance Mismatch
DAC mismatch
0.0
0.1
1.0
SNDR (dB)
73.15
57.80
38.00
Individual Level Averaging off
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Results-Capacitance Mismatch
DAC mismatch
0.0
0.1
1.0
SNDR (dB)
73.15
70.40
51.19
Individual Level Averaging on
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Results-Thermal Noise
Temperature
-30oC
27oC
100oC
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Results-Thermal Noise
Capacitor sizes
1X
2X
4X
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Results-Jitter Noise
Jitter models
Sampling deviation 70.7128 dB
Derivative 70.4322 dB
0.4 relative difference
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Results-Jitter Noise
Jitter standard deviations
0.0 ns
0.1ns
1.0 ns
Input of 62 kHz
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Results-Jitter Noise
Jitter standard deviations
0.0 ns
0.1ns
1.0 ns
Input of 120 kHz
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Comparison with Previous Models

• Low power case
• Smaller Io
• Smaller DC gain
• Inclusion of go

Traditional Model
Presented Model
Admittance Matrix
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Speed
Cycles Admittance Matrix Model VHDL-AMS Transient Model
8192 31 min 42 sec 15 sec
16384 1 hr 4 min 42 sec 30 sec
32768 2 hr 12 min 8 sec 1 min
65536 4 hr 13 min 5 sec 2 min 11 sec
A robust algorithmic-level time complexity
analysis is difficult!
Simulations were carried on a Pentium 4 PC with
2GB memory running at 3.0GHz.
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Conclusions

• An accurate model of a second-order multi-bit S??
  was developed
• Addresses several non-idealities such as
• Jitter Noise
• Thermal Noise
• Capacitance Mismatch
• Integrator dynamics
• The integrator model an improved behavioral
  characterization of the degrading effects of
  settling errors on high-speed S??s

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Conclusions

• Results against SPICE simulations show errors
  less than 7
• Results for GSM (200kHz) show 2.78 of error
• Results for WCDMA (2.0 MHz) show 2.41 of error
  in comparison with 15 for the previous model
• Behavioral modeling and simulation with VHDL-AMS
  is a viable solution to the extensive
  transistor-level simulation of S??s

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References

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   Behavioral Modeling Methods for
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Acknowledgements

• Dr. Manuel Jiménez
• Dr. Rogelio Palomera
• Dr. Domingo Rodríguez
• Felix O. Fernández
• This work was partially supported by Texas
  Instruments through the TI-UPRM Program.

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Questions?