Title: Characterizing the Effects of Clock Jitter Due to Substrate Noise in DiscreteTime DS Modulators
1Characterizing the Effects of Clock Jitter Due to
Substrate Noise in Discrete-Time DS Modulators
- Payam Heydari
- Department of Electrical Engineering and Computer
Science - University of California, Irvine
- CA 92697-2625
DAC 2003, Anaheim, CA June 2-6, 2003
2Outline
- Introduction
- Overview of DS Modulation
- Substrate Noise Characterization
- Clock Jitter Due to Substrate Noise
- Impact of Clock Jitter on DS Modulators
- Experimental Setup
- Experiment PLL Clock Jitter
- Experiment SNR of the DS Modulator
- Conclusions
3Introduction
Analog
Digital
A/D
D/A
p- Epitaxial Layer
p Substrate
- Substrate coupling degrades analog signal
integrity, especially during clock transitions - induces timing jitter in phase-locked-based
on-chip clock generators - degrades the signal-to-noise ratio of data
converters
4Introduction
- DS modulation is a ubiquitous technique widely
used in mixed-signal integrated circuits
DS Modulator
Filter
S/H
Filter
OSR
PFD/CP
Filter
VCO
A/D
DS Modulator
D/A
OSR
Filter
Filter
DS Modulator
K
D/A
Fractional-N Frequency Synthesizer
Oversampling Data Converters
Discrete-time(DT)
DS Modulator
Continuous-time(CT)
5Overview of DS Modulation
yn
un
HDS(z)
vn
- Reshapes the quantization noise over the
frequency band of interest, and enhances the
signal-to-noise ratio (SNR)
- Susceptible to substrate noise
6Substrate Noise Characterization
- An efficient model for substrate coupling is
developed - Contains the statistical nature of the switching
activity - Germane to epi-type heavily doped substrate
- Less accurate compared to 3D models
- Can be incorporated in the PLL as well as DS
modulator circuit
Assumption D. K. Su et al., JSSC93
- Heavily doped bulk exhibits a negligible
electrical resistance - Therefore, modeled as a single electrical node
- The spacing between the circuit blocks causes
only a random phase shift on the noise
fluctuations.
7Substrate Noise Characterization
VDD
n
n
p
p
p
n
n-well
p- Epitaxial Layer
p Substrate
VDD
ZVDD,k
.
ZP1
ZP2
ZPn
ZW1
ZW2
ZWn
CD
.
ZL1
ZL2
ZLn
vsub(t)
.
ZN2
ZN,n
ZN1
ZSUB1
ZSUB2
ZSUB,n
.
ZGND,k
8Substrate Noise Characterization
Substrate noise for a complete one-cycle
simultaneous switching of buffers
vsub,P(t)
vsub,N(t)
- Goal
- Providing simple analytical model for substrate
noise - Such analytical model will be utilized to
investigate the impact of clock jitter induced by
substrate noise on DS modulators
9Substrate Noise Characterization
- Caused by random switching of switching circuits
in a chip - The switching activity of a large digital block
is a function of the nature and the statistics of
the input signals - Substrate noise is thus a stochastic process
vsub,P(t)
vsub,N(t)
10Substrate Noise Characterization
- gn and ln are uniformly distributed independent
random processes - Circuits switch randomly across the chip
- Random switching of circuits located at different
locations across the chip are translated to
random signal propagation delays
R. Schreier et al., JSSC, Dec02,
pp. 1636-1644
11Substrate Noise Characterization
ts,P , ts,N ltlt T/2
ts,N
ts,P
- Substrate noise is modeled as an impulse train
with normally distributed random area, and
uniformly distributed random time-shift
VCLK , vsub,N(t), vsub,N(t)
t
12Substrate Noise Characterization
- Theorem
- Consider the following wide-sense
cyclo-stationary stochastic process - where An is a discrete-time random-process.
The shifted process z(t), given below - is a wide-sense stationary process, whose power
spectral density (PSD) is
13Clock Jitter Due to Substrate Noise
- The operation of a switched-capacitor DS
modulator depends on the complete charging or
discharging during each phase of the clock. - The effects of clock jitter induced by substrate
noise on a switched capacitor circuit can be
analyzed by examining its effect on the sampling
of the input signal - These effects are independent of the structure or
order of the modulator.
- Related Work
- Analysis of PLL timing jitter P. Heydari et al.,
CICC00 A. Hajimiri et al., 1999 - Jitter and phase noise in free-running
oscillators A. Hajimiri et al., 1999 A. Demir,
DAC98
14Charge-Pump PLL (CP-PLL)
LPF
IN
Phase/Frequency Detector
w
VCO
OUT
FVCO
- The VCO is the most noise-sensitive circuit among
other sub-blocks - High-pass behavior for the VCO phase noise
w
15CP-PLL Jitter Due to Substrate Noise
- The VCO phase noise analysis is carried out by
studying a simple conventional differential delay
stage
VDD
- Each delay stage is a neutralized differential
circuit - Differential operation enhances the VCO noise
performance - Nonetheless, large-signal operation still
influences the VCO sensitivity to substrate noise
Replica Biasing
CD
CD
CL
CL
Vid
ISS
Vcont
CD
CD
- Substrate noise
- Control path
- Direct coupling
CL
CL
Vid
Vcont
16CP-PLL Jitter Due to Substrate Noise
Substrate Noise
DIoID1- ID2
ID1
ID2
w1(t)
DIo
Vid
DISS,noise
DISS,noise
Vm
vVCO(t)
-Vm
w1(t)
17CP-PLL Jitter Due to Substrate Noise
- Holds true for any arbitrary ring VCO topology
- Remember that vsub(t) is a stochastic process
- We need to determine the autocorrelation and PSD
of the time-average of the excess phase DFVCO
IPD
LPF
IN
Phase/Frequency Detector
w
IPD
VCO
18CP-PLL Jitter Due to Substrate Noise
- A general noise analysis of the PLL is carried
out using the Fokker-Planck stochastic
differential equations - Assumption
- Substrate noise induces timing jitter at the PLL
output without unlocking the loop
PLL phase noise
Digital Oscope
sDF(T)
Tclock
PLL
Input
Trigger
DT
19Impact of Clock Jitter on DS Modulators
en
yn
un
HDS(z)
vn
- In the presence of clock jitter
20Impact of Clock Jitter on DS Modulators
- The spectrum of the jitter induced output error
is
DwBW
w
w
- The total jitter induced noise power of the DS
modulator is the area under the PSD curve
21Impact of Clock Jitter on DS Modulators
- The jitter induced noise at the output of the SD
modulator - decreases with the oversampling-ratio (OSR)
- increases with the noise gain of the VCO
- increases with input frequency as well as input
amplitude - decreases with the charge-pump current and the
resistor of the loop filter
22Experimental Setup
- A conventional differential second-order SD
modulator is designed in 0.25mm CMOS process
Vref
Vref -
C2
C2
S2
S2
S3
S3
S1
S1
C1
S4
S4
C1
Vout
Latched comparator
Sq
Sq
Vin
S1
C1
C1
S4
S4
S1
S3
S2
S2
S3
C2
C2
Vref
Vref -
- The clock is provided by a CMOS PLL with a lock
range of 1MHz-500MHz - The PLL circuit architecture is similar to the
one proposed in Maneatis, JSSC96
23Experimental Setup
- To experimentally emulate the switching of
digital circuits, 40 tapered inverters driving
1pF capacitors are placed around the PLL - To maximally dampen the direct substrate coupling
on the sampling network, physical separation is
provided between the second-order DS modulator
and the noisy digital circuit - To account for the randomness of the switching
activity of digital circuits, the input signals
to the tapered buffers are generated by a
pseudo-random generator with a Gaussian
distribution.
24Experiment PLL Clock Jitter
X Simulation
- Analytical Model
25Experiment PLL Clock Jitter
0.16V2
0.16V2
0.04V2
0.04V2
0.01V2
0.01V2
X Simulation
X Simulation
- Analytical Model
- Analytical Model
Overdamped
26Experiment PLL Clock Jitter
0.12V2
0.12V2
X Simulation
X Simulation
- Analytical Model
- Analytical Model
0.04V2
0.04V2
0.01V2
0.01V2
Overdamped
27Experiment SNR of the SD Modulator
No substrate noise injection
X Simulation
- Analytical Model
With substrate noise injection
28Experiment SNR of the SD Modulator
X Simulation
- Analytical Model
fin 400kHz
fin 300kHz
fin 200kHz
fin 100kHz
fin 50kHz
29Conclusions
- The effects of clock jitter induced by substrate
noise in discrete-time DS modulators was studied.
- A new stochastic model for substrate noise was
proposed. - This model was utilized to study the clock jitter
in PLL clock generators. - Next, the effect of clock jitter on the
performance of the DS modulator was studied. - A circuit consisting of a second-order DS
modulator, a charge-pump PLL, and forty
multistage tapered inverters driving 1pF
capacitors was designed in a 0.25mm standard CMOS
process. - Several experiments on the designed circuit
verified the high accuracy of the proposed
analytical models.