Apresenta

1
Logic Synthesis in IC Design and Associated
Tools Introduction
Wang Jiang Chau Grupo de Projeto de Sistemas
Eletrônicos e Software Aplicado Laboratório de
Microeletrônica LME Depto. Sistemas
Eletrônicos Universidade de São Paulo
2

• SOCs

• Embedded Systems

• Integrated Circuits

• Digital Systems

3
Example 405 PBD Platform
4
Three key embedded system technologies

• Technology
• A manner of accomplishing a task, especially
  using technical processes, methods, or knowledge
• Three key technologies for embedded systems
• Processor technology
• IC technology
• Design technology

5
Processor technology

• The architecture of the computation engine used
  to implement a systems desired functionality.
• Processor does not have to be programmable.

Datapath
Controller
Datapath
Controller
Datapath
Controller
Control logic
index
Registers
Control logic and State register
Control logic and State register
Register file
total
Custom ALU
State register

General ALU
IR
PC
IR
PC
Data memory
Data memory
Program memory
Program memory
Data memory
Assembly code for total 0 for i 1 to
Assembly code for total 0 for i 1 to
General-purpose (software)
Application-specific
Single-purpose (hardware)
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Processor technology

• Processors vary in their customization for the
  problem at hand.

total 0 for i 1 to N loop total
Mi end loop
Desired functionality

General-purpose processor
Single-purpose processor
Application-specific processor
7
IC technology- 1

• Three types of IC technologies
• Full-custom/VLSI
• Semi-custom ASIC (gate array and standard cell)
• PLD (Programmable Logic Device)

8
IC technology- 1

• Semi-custom design styles and implementation

semicustom
Cell-based (all masks)
Array-based

• Macro cells
• Memory
• PLA
• Gate matrix,

• Pre-wired
• Anti-fuse based
• Memory-based

• Pre-diffused
• Gate arrays
• Sea of gates
• Compacted arrays

Standard cells Hierarchical cells
9
Design Technology

• The manner in which we convert our concept of
  desired system functionality into an
  implementation.

10
Moores law

• The most important trend in embedded systems.
• Predicted in 1965 by Intel co-founder Gordon Moore

Note logarithmic scale
IC transistor capacity has doubled roughly every
18 months for the past several decades
11
Design productivity gap

• While designer productivity has grown at an
  impressive rate over the past decades, the rate
  of improvement has not kept pace with chip
  capacity.

12
Design productivity gap

• 1981 leading edge chip required 100 designer
  months
• 10,000 transistors / 100 transistors/month
• 2002 leading edge chip requires 30,000 designer
  months.
• 150,000,000 / 5000 transistors/month
• Designer cost increase from 1M to 300M.

13
The modeling of the design flow- 1
The Y- Diagram
14
The modeling of the design flow- 2
Behavioral Domain
Structural Domain
Communicating processes
Systems
Processors
Algorithms
Register Transfers
ALUs, RAM, etc.
Logic
Gates, flip-flops, etc.
Transfer function
Transistors
Transistor level
Cell layout
Module Layout
Floorplans
Physical Partitions
Physical Domain
15
The modeling of the design flow- 3
Levels and Domains
16
System Level
Structural
Behavioral
Models of Computation (MoCs)
Algoritms (and languages) for Finite State
Machine or HCFSM Petri-nets Concurrent Process
(channels and processes) Data-flow, etc.

• very abstract (no implementation details)
• No notion of Hw or Sw
• efficient to get a compact execution model as
  first design draft

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Algorithmic Level
Structural
Behavioral (related to HW)
SW
0 int x, y 1 while (1) 2 while
(!go_i) 3 x x_i 4 y y_i 5 while
(x ! y) 6 if (x lt y) 7
y y - x else 8
x x - y 9 d_o x
CCD preprocessor
A2D
Microcontroller
JPEG codec
DMA controller
Memory controller
UART
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Register Transfer Level
Structural
Behavioral
begin wait until clock'event and clock'1'
If reset'1' then RegWrite_D1 '0'
RegWrite_D2 '0' RegWrite_D3
'0' Video_Write_D '0' RegWrite_D
lt '0' Else Regwrite_D3
RegWrite_D2 RegWrite_D2 RegWrite_D1
RegWrite_D1 RegWrite ....
19
Gate Level
Behavioral
Structural
SC_MODULE(nand2) sc_inltboolgt A, B
sc_outltboolgt F
void do_nand2() F.write( !(A.read()
B.read()) ) SC_CTOR(nand2)
SC_METHOD(do_nand2) sensitive ltlt A ltlt B

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Transistor Level
Behavioral
Structural
21
The synthesis flow
The behavioral and structural sequencing
22
Optimization Trade-Off in CombinationalCircuits
23
Optimization Trade-Off in SequentialCircuits
24
The simulation flow
from untimed to timed
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Synthesis Application of Optimization Technology
processor allocation HW/SW partitioning process/ta
sk scheduling
System Synthesis
Algorithmic Synthesis (High-level synthesis)
pipelining scheduling resource allocation
state machine optimization multi-level logic
minimization technology mapping
Logic Synthesis
clock tree design optimal placement global/detaile
d routing
Layout Synthesis
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Logic Synthesis Definition- 1

• Wide Interpretation
• Automatic conversion of a hardware description
  language (HDL) model into a gate-level netlist,
  which meets a set of design criteria (area,
  speed, testability, design rules, etc.)

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Logic Synthesis Definition- 2

• Narrow Interpretation
• Translation
• transform logic-level HDL into Boolean
  equations and latches
• Logic optimization
• reduce the area and/or delay of the equations by
  modifying the
• equations and latches
• Technology mapping
• implement the equations and latches by choosing
  gates from a
• fixed library of primitive elements
• Logic synthesis is a set of techniques to assist
  a logic designer in producing
• a high quality logic design quickly and
  efficiently

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Logic Synthesis?
Finite-State Machine F(X,Y,Z, , ) with
X Input alphabet Y Output alphabet Z Set of
internal states X x Z Z (next state
function)? X x Z Y (output
function)?
Circuit C(G, W) with G set of circuit
components (cells, gates,
flip-flops, etc)? W set
of wires connecting components of G
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Sequential Logic Synthesis
Finite-State Machine F(X,Y,Z, , ) with
State Minimization
State Assignment
X
Y
Circuit composed of Combinational logic for
and Set of registers (flip-flops) D
D
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Combinational Logic Synthesis
X
Y
Combinational logic for and
D
Cells, gates and flip-flops

31
Steps of Combinational Logic Synthesis
Two-level minimization
z,Y f (x, y) Combinational Logic
z
x
Y
y
Removing the Registers
Multi-level optimization
z
x
x
Y
Y
y
y
Technology mapping
Removing the Registers
Removing the Registers
32
Objective Function for Synthesis

• Minimize area
• in terms of literal count, cell count, register
  count, etc.
• Maximize performance
• in terms of maximal clock frequency of
  synchronous systems, throughput for asynchronous
  systems
• Minimize power
• in terms of switching activity in individual
  gates, deactivated circuit blocks, etc.

33
Constraints on Synthesis

• By implementation style
• two-level implementation (PLA)
• multi-level logic
• FPGAs
• By performance requirements
• minimal clock speed requirement
• minimal latency, throughput
• By cell library
• set of cells in standard cell library
• fan-out constraints
• cell generators

34
Logic Synthesis Advantages

• Design capture at the register transfer level
  (RTL) and logic level using HDLs
• Technology independent design description
• Easy reuse of old designs
• Designer focus is at the architectural level, not
  the gate level
• Automates tedious gate-level design phase
• Allows designer to explore architectural changes
  quickly
• Logic optimization to implement the design at the
  gate-level
• Optimizes design for a specific ASIC technology
  and library
• Optimization is essential to produce competitive
  designs

35
Instability of Logic Synthesis