Modeling flow and models improvement for I3T ON Semiconductor technologies Petr Betak, Petr Zavrel, Lenka Sochova, Jan Plojhar

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Modeling flow and models improvement for I3T
ON Semiconductor
technologiesPetr Betak, Petr Zavrel, Lenka
Sochova, Jan Plojhar

• MOS-AK September 2011

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Overview

• OVERVIEW ON technologies
• WHAT IS MODELING
• GENERAL FLOW IN MODELING
• Data For Modeling Purpose
• Built up model card as a subcircuit
• DEVICES (focus on I3T80 I3T50)
• CMOS
• DMOS
• BIPOLARS
• DIODES
• RESISTORS
• CAPACITORS
• SPECIAL CASES, MODEL IMPROVEMENT

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Overview ON technologies
Bipolar BIP14V, BIP18V, BIP30V, BIP50V, ON50
... BCD ONC25 (0.25um) , PS5, AIM Analog CMOS
ACMOS, ONC110 (0.11um), ONC18 (0.18um),
ONC25(0.25um) VHVIC (very high voltage) analog
CMOS BCDMOS I2T100 (0.7um)
I3Txx I3T25, I3T50, I3T80 (0.35um)
C3, C5 (0.35um, 0.5um) Special Low Vf
Rectifiers, Integrated Power devices, HV FET,
Microintegration ...
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WHAT IS MODELING?

• DEVICE MODEL - set of mathematical relations
  between node voltages and terminal currents
• GOAL - accurately represent electrical behavior
  in circuit simulators
• DEPENDEND ON DIFFERENT KIND OF PARAMETERS
• technology parameters
• geometry (layout) parameters
• empirical (fitting) parameters

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GENERAL FLOW IN MODELING
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Data For Modeling Purpose

• DC MEASUREMENT DATA measured on golden
  wafers of different lots
• IV curves, transforms
• temperature sweeps
• different dimensions (W,L matrix)

• CV MEASUREMENT DATA measured on golden
  wafers of different lots
• CV curves, junction capacitances
• frequency sweeps
• different dimensions (W,L matrix)

• S PARAMETERS DATA measured on golden
  wafers of different lots
• capacitance extraction
• high frequency verification

• NOISE measurement, matching extraction ...
  

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Built up model card as a subcircuit
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I3T80 I3T50 DEVICES

• Short overview of model features limitations
  per device groups
• Low Voltage MOS
• High Voltage MOS
• Bipolar Transistors
• Diodes
• Resistors
• Capacitors

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Low Voltage MOS

• Model Features
• BSIM 3v3, BSIM4 model
• SOA, Matching
• DC (geom., temp., leakage)
• AC (CV 1/f noise)
• Multi-fab / process corners
• Verified till 200C
• Model Limitations
• Moderate/weak inversion inaccuracy
• Incapable of RF modeling
• Pocket Diode
• NEPI-to-PSUB (NLVD, NMVD)

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High Voltage MOS
DEVICE

• Model Features
• JFET(J1) for drift region (model IDSAT Ron)
• Standard BSIM3v3 dominant MOS (M1) model
  channel part (VTH BETA)
• AC behaviour modelled by dominant MOS added
  shorted MOSFETs (M2 M3)
• Parasitic diode integrated in subcircuit
• Formula for BLN res.
• SOA, Matching
• Verified till 200C
• 1/f noise
• Limitations
• No parasitic BJT
• No self-heating
• AC modelled at 100kHz
• Pocket diode
• NEPI/BLN-to-PSUB

MODEL
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MOS DMOS

• DC MODELING
• IDVG over temp. and over size
• VTH, short narrow channel effect
• Body effect
• IDVD over temp. and over size
• IDSAT RON over size

NMOS short channel effect
Ron
IDSAT
lfpdm80 output curves
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MOS DMOS

• AC
• Cgs,
• Cgd over size
• for different
• VG VD

• Vth Beta Matching

INTRINSIC MOSFET
ACCUMULATION MOSFET

• 1/f noise

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Bipolar Transistors

• Model Features
• VBIC (NPN) model BJT (PNP)
• Vertical devices
• Checked till 200C
• DC
• Gummel Poon ( Beta vs. Ic)
• Output characteristics ( Early Voltage)
• Validated on band-gaps (?VBE tuned)
• Base-emitor breakdown and parasitic PNP (for NPN)
• AC
• diffusion and depletion capacitances

• Matching
• Model Limitations
• No S-param validation
• No 1/f noise

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Diodes / Junctions

• Model Features
• DC
• - forward
• - Breakdown leakage
• - done for -30C till 200C
• AC (capacity modelled)
• SOA
• Based on diode, dio500 standard models
• Model Limitations
• Transit-time modelcharged based model, not
  accurate enough
• Parasitic bipolar not modelled
• Snap-back not modelled for ESD diodes

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Resistors

• Model Features
• POLY ,Diff. Resistors ,METAL RESISTORS
• matching based on Pelgrom formula for resistance
  std. deviation
• based on phy_res, resistor, bsource standard
  models
• verified form -40C till 200C
• Model Limitations
• TC not modelled over corners over size
• TC based on typical silicon, only PPOR
  statistically verified

sheet res.
temperature dep.
correction
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Capacitors

• Model features
• MIM capacitor, metal to metal cap., horizontal
  bar plate cap.
• Voltage linearity and temperature dependency
  model (TC)
• Scalable according the bar, width length
• Verified till 125C
• SOA implemented
• Model limitations
• no matching in the models
• minimum dimension of device at least 10um
• resistance self inductance not included

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Special cases, model improvement
Model conversion into different simulator
language SPECTRE, ELDO, HSPICE -gt HSPICE model
of the physical resistor Modeling of the
substrate current and recovery charge JUNCTION
DIODES -gt Enhanced NQS Lauritzen diode model
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HSPICE model of the physical resistor
Circuit connection of the model elements in
HSPICE for SPECTRE subtypep
Circuit connection of the model elements in
HSPICE for SPECTRE subtypepoly
Circuit connection of the model elements in
HSPICE for SPECTRE subtypen
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HSPICE model of the physical resistor
Example of the Physical resistor conversion
Comparison of the SPECTRE and HSPICE results
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ENHANCED NQS LAURITZEN DIODE MODEL

• MAIN DIODE
• NQS diode verilog model for AK diode
  (dioAREAmain and dioPERImain)
• substrate current source model IPsubf(IA)
• breakdown diode (SPICE)

• PARA DIODE (POCKET DIODE)
• NQS diode verilog model for KPsub diode
• current source model lAPsubf(IPsub)
• breakdown diode (SPICE)

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ENHANCED NQS LAURITZEN DIODE MODEL
Reverse recovery effect modeling
Extraction of diffusion capacity
The indirect approach of tuning and measuring
reverse recovery effect consists in measuring
S-parameters and extraction of a diffusion
capacitance of forward biased diode in the area
of threshold voltage region (OFF state to ON
state) with the voltage step of 5 mV 3.
Comparison of current in time during recovery for
measured diode (ia.m - blue) and NQS Lauritzen
updated model (ia.s - cyan)
NQS updated Lauritzen model (blue) vs. measured
(extracted) diffusion capacity (cyan)
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Current source model
ENHANCED NQS LAURITZEN DIODE MODEL

• 
  
• The current added by PARA DIODE to MAIN DIODE
  IAsubg(IPsub) is lower level of magnitude, ca.
  0.1 of MAIN DIODE IA stream ad is of same model
  where n -66e-6 m5.163

• The current source IPsub
• model of the substrate current dependent on
  current flowing through the MAIN DIODE(IA)
• expressed by (1), where m1.606 and n -5e-3 are
  variables to tune the current behavior,
  determined based on measurement data
• 
  

Conclusion

• The proposed macro-model of diode enhances the
  standard diode model by adding Lauritzen NQS
  model of reverse recovery effect and the model of
  the diode cathode-to-substrate junction.
• The updated macro-model of the diode visibly
  improves reverse recovery effect simulation
  results.
• The proposed model of substrate current also fits
  well the measured data as well as reverse current
  from measured at the substrate node.
• What is also positive point, the updated NQS
  model of investigated diode do not leads to
  convergence problem and do not increase
  simulation time.

(1)
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REFERENCES
1 P.O Lauritzen, C.L. Ma, A Simple Diode
Model with Reverse Recovery, IEEE Transaction on
Power Electronics, Volume 6, Issue 2, April 1991,
pp. 188-191 2 Sauter Martin, Reverse Recovery
Effects in SPT5 Diodes, Infineon Technologies
papers, IC-CAP Modeling Handbook, internet
source http//edocs.soco.agilent.com/pages/viewpa
ge.action?pageId105321342 3 Sischka Franz,
IC-CAP Learning Week, Agilent Technologies,
EEsoft EDA Europe, May 2010 4 A.Vladimirescu,
The Spice Book New Yorl, 1994, John Wiley Sons,
Inc 5 Cadence Circuit Components and Device
Models Manual Product Version 6.1, December 2006,
CADENCE 6 HSPICE Reference Manual Elements
and Device Models Version C-2009-09, September
2009,. SYNOPSYS 7 ELDO Userss Manual Software
version 6.10_2 Release AMS 2007.2a, 2007,. MENTOR
GRAPHICS CORP. 8 Stanislav Banas, et al.
Enhanced NQS Lauritzen Diode Model, MIXDES,
2011, Proceedings of the 18th International
Conference, pp. 82-84