SRAM A-Factors for Simple 6T SRAM Cell using Microprocessor Logic CMOS Process Technology

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SRAM A-Factors for Simple 6T SRAM Cell using
Microprocessor Logic CMOS Process Technology
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F, Company, Reference
A factor
0.15, TSMC, VLSI00 152
0.13, Toshiba, VLSI00 148
0.18 (0.13 poly), Motorola, VLSI00, embedded! 85 (or 162 using 0.13)
0.13, IBM, SOI, VLSI00 128
0.13, IBM, bulk, VLSI00 147
0.18, TSMC, VLSI99 136
0.18, IBM, VLSI99 119
0.18, IBM, ISSCC00 131
0.25, UMC, IEDM97 101
0.25, Samsung, VLSI98 102
0.13, Fujitsu, VLSI98 0.25, Motorola, VLSI98 147 150
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Virtual Silicon libraries based on United
Microelectronics (UMC) processes A-factors 0.25
mm, high-performance (10 tracks)2-in NAND/NOR
371INV 248MUX2 867DFF 2106 0.18 mm,
high-performance (11 tracks), quoted max density
93.5K gates/mm2, translating to 10.7 mm2/gate
or 330F2 2-in NAND/NOR 377INV 251MUX2
878DFF 2133 0.15 mm, high-density (8 tracks),
about 20 smaller than high-performance, quoted
max density 173K gates/mm2, translating to 5.8
mm2/gate or 258F2. 2-in NAND/NOR 307INV
205MUX2 717DFF 1638
If we assume contacted metal pitch 2.5F (e.g.
MP 0.625 mm for 0.25 mm), this gives 60 MP2
for 2-in NAND/NOR, which is inline with BACPAC
calcs
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Current recommendations SRAM cell size
150-160F2 Std. Cell size 375F2?? SRAM overhead
use factor of 1.6 (60 overhead penalty) These
areas dont include any white-space consideration
so the actual packing density should be lower