Lect 3: Real Addressed Mode S/W Architecture of the 80386DX Microprocessor

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Lect 3 Real Addressed Mode S/W Architecture of
the 80386DX Microprocessor
2
386DX Microprocessor

• Internal Architecture
• page 18, Fig 2.1
• Features
• Flexible 32-bit Microprocessor
• 8,16,32-bit Data Type
• 8 GPR (32-bit)
• Very Large Address Space
• 4 GB Physical
• 64 Terabyte Virtual
• 4 GB Maximum Segment Size
• Integrated Memory Management Unit
• VM support
• Operational On-chip Paging
• 4 Levels of Protection
• Fully Compatible with 80286

3

• Features
• Real Address Mode, Protected Mode, Virtual 86
  Mode
• Optimized for System Performance
• Pipelined Instruction Execution
• On-chip Address Translation Caches
• 20, 25, and 33 MHz clock
• 132 pin Grid Array Package

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Real-Mode Software Architecture

• reset -gt real mode object code compatible with
  8086
• Real-mode software model page 21, figure 2.2
• Reset and Initialization
• starting address FFFFFFF0H
• after the first Intersegment Jump or Call,
  A20-A31 will drop low
• Flag Word UUUU0002H MSW(CR0) UUUUUUU0H
• IP 0000FFF0H CS FFF0H
• DS,SS,ES,FS,GS 0000H DX Component and
  stepping ID
• all other registers undefined
• Real-Mode Memory-Address Space and Data
  Organization(2.4)
• 80386DX Real-Mode 1MB of external memory
• 1 MB address space 8086 address space

FFFFFH
pointer
segment base
general
400H
3FFH
dedicated(interrrupt service vector table)
0
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Real-Mode Software Architecture

• 16-bit word access
• Byte, Word, Double Word Accesses
• no alignment
• aligned double-word addresses are multiples of 4
• unaligned(mis-aligned) double-word
• Data Types (2.5)
• Fundamental Data Format byte, word, double word
• Integer
• unsigned byte, word, double word signed
  byte, word, double word
• BCD(binary-coded decimal) numbers packed,
  unpacked
• ASCII

1
0
0
0
Little Endian (DEC, Intel)
0
1
Big Endian (IBM, Motorola)
3
3
2
2
2
2
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Segment Registers and Memory Segmentation (2.6)

• 64 KB segments 1 MB of memory
• CS(code segment) SS(stack segment) DS(data
  segment) ES(extra segment) FS, GS (data segment
  F, G)
• 6 segments total of 384 KB active memory 64 K
  for a code, 64 K for a stack, 256 K for data
  storage
• segments can be set up to be contiguous,
  adjacent, disjoint, or even overlapping
• segment base addresses multiple of 4H (4 digit
  shift left)
• page 31, fig 2.12 page 31, fig 2.13
• Instruction Pointer (2.7)
• 16-bit IP in real mode
• next code address CSIP
• General Purpose Data Registers (2.8)

EAX
Accumulator (A) ASCII Adjust, ......
AX
AH
AL
Base (B) table-lookup translations
Count (C) loop operations, repeat string
operations, shift/rotate
Data (D) indirect I/O, I/O string, Multi, Divide
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Pointers and Index Registers (2.9)

• two index registers (ESI, EDI) and two pointer
  registers (EBP, ESP) page 34, fig 2.15
• contains offset addresses (16-bit in real mode
  64 KB)
• ESP(extended stack pointer) and EBP(extended base
  pointer)
• combined with the contents of the SS register to
  produce physical memory address
• TOS (top of stack) SSSP
• BP an offset relative to the SS register
• ESI (extended source index register) and EDI
  (extended destination index register)
• automatically combined with the value in the DS
  register
• FLAGS REGISTER (2.10)
• 32-bit flags just nine of its bits are active in
  the real mode
• Carry flag(CF) carry-out, borrow-in
• Parity flag (PF) set if even parity
• Auxiliary carry flag (AF) carry-out from the
  low nibble
• Zero flag(ZF) arithmetic or logic 0
• Sign bit (SF) sign
• Overflow flag (OF) the signed result is out of
  range
• Trap flag (TF) single step mode
• Interrupt flag (IF) maskable interrupt requests
• Direction flag (DF) string operation when set,
  the string ops automatically decrements the
  address.

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Generating A Real-Mode Memory Addresses (2.11)

• Real-mode physical address generation page 36,
  fig 2.17
• Segment-override prefix
• change the segment from which the variable is
  accessed.
• CS and SS alternate seg none
• variables, string sources default DS alternate
  seg ES, FS, GS, SS, CS
• string destination ES alternate seg none
• BP used as base register default SS alternate
  seg ES. FS, GS, DS, CS
• BX used as base register default DS alternate
  seg ES, FS, GS, SS, CS
• Example page 38, fig 2.19, fig 2.20

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Stack (2.12)

• Call, Return, Push and Pop instructions
• In the real mode, the stack is 64 K long
• stack structure page 40, Fig 2.22 page 42, Fig
  2.24
• Real-Mode Input/Output Address Space (2.13)
• Seperate memory and Input/Output address spaces
• 64KB I/O address space
• page 0 0000H through 00FFH --gt direct I/O
• indirect addressing DX register
• See page 43, Fig 2.25