Survey of Discrete Cosine Transform Implementations and Example Hardware 1-D DCT/IDCT Implementation

1
Survey of Discrete Cosine Transform
Implementations andExample Hardware 1-D
DCT/IDCT Implementation

• Vijay Sundar Srinivasan
• Electrical and Computer Engineering
• ECE734 Fall 2000 Project

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Project Goals

• Survey (deliverable - report)
• Brief description of where DCT fits into image
  processing and how 1-D DCT often forms core of
  fast 2-D DCT implementations
• Quantitative comparisons between 4 types of HW/SW
  1-D DCT implementations based on 4 criteria
• Implementation (deliverable - design schematic)
• 8-point 1-D Discrete Cosine Transform
• Direct computation of formula, design entry in
  Vhdl schematic

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Approach for Survey

• Main information resource internet
• Comparison categories
• Performance Speed/Power/Area/Precision
• Implementation GPMicroprocessor(S/W),DSP based,
  FPGA-HDL based/ ASIC based
• Comparison considerations

precision
power
speed
-data format I/P O/P resolution, internal
resolution
-Voltage -Complexity -Switching
-algorithm -architecture (pipelining/DA..)
area
-Component Reduction -feature size
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Implementation

• Schematic entry-gtsynthesis, simulation
  Altera MaxPlusII Baseline 10.0
• Vhdl entry-gtsynthesis Synopsys Fpga Express
• Direct Implementation Multiply-Accumulate
• Altera library components used (multiplier/rom/add
  er)
• Control block in Vhdl

X(70)
1-Dimensional DCT/IDCT
Y(70)
Enable
Start
Clk
Ready
Rst
Idct
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Progress / Schedule / Improvements

• Survey data is being collected on all types of
  DCT implementations and categorized
• Implementation Appropriate Altera devices are
  being studied for best speed currently datapath
  is being put together using Altera components
• Further tentative improvements Precision,
  Pipelining
• Forecast Completion in the first half of
  January 2001