Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs

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Analytical Approach for Soft Error Rate
Estimation of SRAM-Based FPGAs
Ghazanfar (Hossein) Asadi Ghazanfar (Hossein) Asadi


Test Reliability Group (TRG) Department of
Electrical Computer Engineering Northeastern
University

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Problem Statement

• Estimating soft error rate in FPGAs
• The probability of system failure
• Due to soft errors
• For a given mapped design
• Mean time to manifest a corrupted conf. bit
• To primary outputs or Flip-flops

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Motivation

• Need for soft error rate estimation
• Exponential growth of vulnerable bits due to
  Moores law
• High cost of Error tolerant schemes
• To make appropriate cost/reliability trade-offs
• Where to put redundancy
• Previous work Fault Injection
• Time-consuming / Incomplete / Expensive
• Needs physical prototype board
• Cannot be used in design phases
• Prototype board can be damaged ? Hard Error

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Error Models in FPGAs

• Memory resources
• User bits
• Flip-flops, RAMs,
• Configuration bits
• Mux select bits, LUT bits, PIPs,
• User bits ? Transient errors
• Config. bits ? Permanent errors

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SER Estimation

• Traversing structural paths Asadi04
• From error sites to outputs

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SER Estimation in ASIC Designs

• S(n) System failure probability (SFP) vector
• Si SFP given node i erroneous
• n total fault sites
• Experiments on ISCAS89 show that
• Three order of magnitude faster
• Compared to random-input simulation
• Accuracy more than 90

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FPGA vs. ASIC in SER Estimation

• ASIC transient error
• Only requires propagation probability
• FPGA both transient permanent errors
• Transient errors the same
• Permanent errors needs activation as well
• More error sites in FPGAs
• Routing signals

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FPGA vs. ASIC in SER Estimation

• Nodes with different error rates in FPGAs
• No attenuation in FPGAs
• During propagation

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SER Estimation of FPGAs Steps

• Compute permanent error rates for all nodes
• PRi the permanent error rate of node i
• n total number of fault sites
• Compute netlist failure probability vector
• Ni failure prob. given node i erroneous
• System failure rate vector (S) PR ? N
• Si PRi ? Ni

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How to Compute Ni?

• Open stuck-at errors
• Ni SPi ? PPi(0) (1-SPi) ? PPi(1) PPi
• PPi Propagation prob. (the method used for ASIC)
• SP Signal probability is used for activation
  prob.
• Bridging wired-AND wired-OR error (nets i and
  j)
• Ni (Wand) SPi?(1-SPj)?PPi(0) (1-SPi)
  ?SPj?PPj(0)
• Ni (Wor) SPi?(1-SPj)?PPj(1) (1-SPi)
  ?SPj?PPi(1)
• LUT bit-flip
• Ni Activation prob. (cell) ? Prop. Prob. (LUT
  output)

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How to Compute PRi?

• PR(n) permanent error rate vector
• PRi r ? f
• r Raw error rate of an SRAM cell
• f Number of all possible errors at node i
• n total number of error sites
• PRAB 6 ? r

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System Failure Rate

• For the first clock
• For c clock cycles
• The same probability is valid for the next clock
  cycles
• c Number of clocks checking the state of the
  circuit
• After particle hit

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Error List

• Mux-open
• PIP open
• Buffer off
• A bit-flip in LUT
• Control/clocking bit-flip

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Experimental Setup

• Xilinx Virtex 300 (XCV300)
• Xilinx Design Language (XDL)
• Benchmark some ISCAS89 circuits
• r raw failure rate for an SRAM cell
• r0.01 FIT/bit
• 1000 clocks executed for each SEU
• Platform Sun Solaris Ultra-10
• 256 MB Main Memory

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Results Sensitive Bits
Number of sensitive SRAM bits for each part
Circuit S27 S298 S344 S349 s382 s386
Routing 64 459 536 650 807 714
LUT 68 418 392 520 712 660
Control/ Clocking 40 140 168 187 207 160
Total 172 1017 1096 1357 1726 1534
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Results SFR Estimation Time
System Failure Rate Estimation Time
Circuit S27 S298 S344 S349 s382 s386
SFR (FIT) 1.71 9.87 9.99 12.77 16.04 12.11
SP Time (sec) 0.15 0.76 0.91 1.09 1.25 1.05
SFR Time (sec) 0.02 0.09 0.13 0.14 0.19 0.25
Total Time (sec) 0.17 0.85 1.04 1.23 1.44 1.30
Number of Clock cycles 1000 SP Time Signal
Probability computation time SFR Time System
Failure Rate computation time
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Results Manifestation Time
Mean Time To Manifest (MTTM) errors to outputs
Circuit S27 S298 S344 S349 s382 s386
Routing 2.07 2.86 2.58 2.91 3.30 3.82
LUT 14.49 20.75 17.33 20.48 22.08 30.07
Control/ Clocking 1.18 1.31 1.36 1.40 1.40 1.77
(Results are in terms of cycles)
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Summary Conclusions

• A new approach for SER estimation
• For SRAM-based FPGAs
• No physical implementation required
• Can be used in early design stages
• Very fast simulation time
• Can cover all possible faults
• Mean Time To Manifest errors to outputs
• MTTM(Control/clocking) lt MTTM(routing)
• MTTM(routing) ltlt MTTM(LUT)

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Questions?

• Thanks