CpE242 Computer Architecture and Engineering Designing a Single Cycle Datapath

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CpE242Computer Architecture and
EngineeringDesigning a Single Cycle Datapath
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Outline of Todays Lecture

• Recap and Introduction
• Where are we with respect to the BIG picture? (10
  minutes)
• The Steps of Designing a Processor (10 minutes)
• Datapath and timing for Reg-Reg Operations (15
  minutes)
• Datapath for Logical Operations with Immediate (5
  minutes)
• Datapath for Load and Store Operations (10
  minutes)
• Datapath for Branch and Jump Operations (10
  minutes)

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Course Overview
Computer Design
Computer Hardware Design Machine
Implementation Logic Designer's View
"Processor Architecture" "Computer
Organization Construction Engineer
Instruction Set Deign Machine Language
Compiler View "Computer Architecture"
"Instruction Set Processor" "Building Architect"
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The Big Picture Where are We Now?

• The Five Classic Components of a Computer
• Todays Topic Datapath Design

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The Big Picture The Performance Perspective

• Performance of a machine was determined by
• Instruction count
• Clock cycle time
• Clock cycles per instruction
• Processor design (datapath and control) will
  determine
• Clock cycle time
• Clock cycles per instruction
• In the next two lectures
• Single cycle processor
• Advantage One clock cycle per instruction
• Disadvantage long cycle time

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Recall the MIPS Instruction Set Architecture
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The MIPS Instruction Formats

• All MIPS instructions are 32 bits long. The
  three instruction formats
• R-type
• I-type
• J-type
• The different fields are
• op operation of the instruction
• rs, rt, rd the source and destination register
  specifiers
• shamt shift amount
• funct selects the variant of the operation in
  the op field
• address / immediate address offset or immediate
  value
• target address target address of the jump
  instruction

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The MIPS Subset

• ADD and subtract
• add rd, rs, rt
• sub rd, rs, rt
• OR Immediate
• ori rt, rs, imm16
• LOAD and STORE
• lw rt, rs, imm16
• sw rt, rs, imm16
• BRANCH
• beq rs, rt, imm16
• JUMP
• j target

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An Abstract View of the Implementation
Clk
PC
Instruction Address
Ideal Instruction Memory
Instruction
Rd
Rs
Rt
Imm
5
5
5
16
Data Address
32
Rw
Ra
Rb
32
Ideal Data Memory
32
DataOut
32 32-bit Registers
Data In
Clk
Clk
32
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Clocking Methodology
Clk
Setup
Hold
Setup
Hold
Dont Care

• All storage elements are clocked by the same
  clock edge
• Cycle Time CLK-to-Q Longest Delay Path
  Setup Clock Skew

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An Abstract View of the Critical Path

• Register file and ideal memory
• The CLK input is a factor ONLY during write
  operation
• During read operation, behave as combinational
  logic
• Address valid gt Output valid after access time.

Clk
Critical Path (Load Operation) PCs
Clk-to-Q Instruction Memorys Access Time
Register Files Access Time ALU to
Perform a 32-bit Add Data Memory Access
Time Setup Time for Register File Write
Clock Skew
PC
Instruction Address
Ideal Instruction Memory
Instruction
Rd
Rs
Rt
Imm
5
5
5
16
Data Address
32
Rw
Ra
Rb
32
Ideal Data Memory
32
DataOut
32 32-bit Registers
Data In
Clk
Clk
32
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Outline of Todays Lecture

• Recap and Introduction (5 minutes)
• Where are we with respect to the BIG picture? (10
  minutes)
• The Steps of Designing a Processor (10 minutes)
• Datapath and timing for Reg-Reg Operations (15
  minutes)
• Datapath for Logical Operations with Immediate (5
  minutes)
• Datapath for Load and Store Operations (10
  minutes)
• Datapath for Branch and Jump Operations (10
  minutes)

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The Steps of Designing a Processor

• 0) Instruction Set Architecture gt
• Register Transfer Language Program
• Convert each instruction to RTL statements
• Register Transfer Language program gt Datapath
  Design
• Determine Datapath components
• Determine Datapath interconnects
• Datapath components gt Control signals
• Control signals gt Control logic gt Control Unit
  Design

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Step 0) Instruction Set Architecture gt
Register Transfer Language ProgramRegister
Transfer Language-RTL The ADD Instruction

• add rd, rs, rt
• memPC Fetch the instruction from memory
• Rrd lt- Rrs Rrt The ADD operation
• PC lt- PC 4 Calculate the next
  instructions address

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RTL The Load Instruction

• lw rt, rs, imm16
• memPC Fetch the instruction from memory
• Addr lt- Rrs SignExt(imm16)
• 
  Calculate the memory address
• Rrt lt- MemAddr Load the data into the
  register
• PC lt- PC 4 Calculate the next
  instructions address

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Step 1) RTL To Data Path Design Data Path
Components,

Combinational Logic Elements
CarryIn

• Adder
• MUX
• ALU

A
32
Sum
Adder
32
B
Carry
32
Select
A
32
MUX
Y
32
B
32
OP
A
32
ALU
Result
32
B
Zero
32
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Step 1) RTL To Data Path Design Data Path
Components, Storage Elements
Register

• Register
• Similar to the D Flip Flop except
• N-bit input and output
• Write Enable input
• Write Enable
• 0 Data Out will not change
• 1 Data Out will become Data In

Write Enable
Data In
Data Out
N
N
Clk
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Step 1) RTL To Data Path Design Data Path
Components, Storage Elements
Register File
RW
RA
RB
Write Enable
5
5
5

• Register File consists of 32 registers
• Two 32-bit output busses
• busA and busB
• One 32-bit input bus busW
• Register is selected by
• RA selects the register to put on busA
• RB selects the register to put on busB
• RW selects the register to be writtenvia busW
  when Write Enable is 1
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, behaves as a combinational
  logic block RA or RB valid gt busA or busB valid
  after access time.

busA
busW
32
32 32-bit Registers
32
busB
Clk
32
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Step 1) RTL To Data Path Design Data Path
Components, Storage Elements
Idealized Memory

• Memory (idealized)
• One input bus Data In
• One output bus Data Out
• Memory word is selected by
• Address selects the word to put on Data Out
• Write Enable 1 address selects the
  memorymemory word to be written via the Data In
  bus
• Clock input (CLK)
• The CLK input is a factor ONLY during write
  operation
• During read operation, behaves as a
  combinational logic block
• Address valid gt Data Out valid after access
  time.

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Step 1) RTL To Data Path Design Data Path
Components, Overview of the
Instruction Fetch Unit

• The common RTL operations
• Fetch the Instruction memPC
• Update the program counter
• Sequential Code PC lt- PC 4
• Branch and Jump PC lt- something else

Instruction Word
32
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Outline of Todays Lecture

• Recap and Introduction
• Where are we with respect to the BIG picture? (10
  minutes)
• The Steps of Designing a Processor (10 minutes)
• Datapath and timing for Reg-Reg Operations (5
  minutes)
• Datapath for Logical Operations with Immediate (5
  minutes)
• Datapath for Load and Store Operations (10
  minutes)
• Datapath for Branch and Jump Operations (10
  minutes)

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Step 1) RTL To Data-Path Design
Determine Data-path interconnectsRTL The ADD
Instruction

• add rd, rs, rt
• memPC Fetch the instruction from memory
• Rrd lt- Rrs Rrt The actual operation
• PC lt- PC 4 Calculate the next
  instructions address

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RTL The Subtract Instruction

• sub rd, rs, rt
• memPC Fetch the instruction from memory
• Rrd lt- Rrs - Rrt The actual operation
• PC lt- PC 4 Calculate the next
  instructions address

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RTL To Data Path Design Data-path for
Register-Register Operations

• Rrd lt- Rrs op Rrt Example add rd, rs,
  rt
• Ra, Rb, and Rw comes from instructions rs, rt,
  and rd fields
• ALUctr and RegWr control logic after decoding
  the instruction

Rs
Rt
Rd
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
Clk
busB
32
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Register-Register Timing
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
RegWr
Old Value
New Value
Register File Access Time
busA, B
Old Value
New Value
ALU Delay
busW
Old Value
New Value
Rs
Rt
Rd
ALUctr
Register Write Occurs Here
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
Clk
busB
32
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Outline of Todays Lecture

• Recap and Introduction
• Where are we with respect to the BIG picture? (50
  minutes)
• The Steps of Designing a Processor (10 minutes)
• Datapath and timing for Reg-Reg Operations (15
  minutes)
• Datapath for Logical Operations with Immediate (5
  minutes)
• Datapath for Load and Store Operations (10
  minutes)
• Datapath for Branch and Jump Operations (10
  minutes)

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RTL The OR Immediate Instruction

• ori rt, rs, imm16
• memPC Fetch the instruction from memory
• Rrt lt- Rrs or ZeroExt(imm16)
• 
  The OR operation
• PC lt- PC 4 Calculate the next instructions
  address

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Datapath for Logical Operations with Immediate

• Rrt lt- Rrs op ZeroExtimm16 Example ori
  rt, rs, imm16

Rt
Rd
RegDst
Mux
Dont Care (Rt)
Rs
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
Result
32
32 32-bit Registers
ALU
32
32
Clk
busB
32
Mux
ZeroExt
imm16
32
16
ALUSrc
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Outline of Todays Lecture

• Recap and Introduction
• Where are we with respect to the BIG picture? (50
  minutes)
• The Steps of Designing a Processor (10 minutes)
• Datapath and timing for Reg-Reg Operations (15
  minutes)
• Datapath for Logical Operations with Immediate (5
  minutes)
• Datapath for Load and Store Operations (10
  minutes)
• Datapath for Branch and Jump Operations (10
  minutes)
• Assignment 3

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RTL The Load Instruction

• lw rt, rs, imm16
• memPC Fetch the instruction from memory
• Addr lt- Rrs SignExt(imm16)
• 
  Calculate the memory address
• Rrt lt- MemAddr Load the data into the
  register
• PC lt- PC 4 Calculate the next instructions
  address

SignExt operation
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Datapath for Load Operations

• Rrt lt- MemRrs SignExtimm16 Example lw
  rt, rs, imm16

Rt
Rd
RegDst
Mux
Dont Care (Rt)
Rs
ALUctr
RegWr
5
5
5
MemtoReg
busA
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
Mux
busB
Clk
32
MemWr
32
Mux
WrEn
Adr
Data In
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc
ExtOp
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RTL The Store Instruction

• sw rt, rs, imm16
• memPC Fetch the instruction from memory
• Addr lt- Rrs SignExt(imm16)
• 
  Calculate the memory address
• MemAddr lt- Rrt Store the register into
  memory
• PC lt- PC 4 Calculate the next
  instructions address

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Datapath for Store Operations

• MemRrs SignExtimm16 lt- Rrt Example sw
  rt, rs, imm16

Rt
Rd
RegDst
Mux
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
MemWr
busA
Rw
Ra
Rb
busW
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32 32-bit Registers
ALU
32
32
Mux
busB
Clk
32
32
Mux
WrEn
Adr
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
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Outline of Todays Lecture

• Recap and Introduction
• Where are we with respect to the BIG picture? (10
  minutes)
• The Steps of Designing a Processor (10 minutes)
• Datapath and timing for Reg-Reg Operations (15
  minutes)
• Datapath for Logical Operations with Immediate (5
  minutes)
• Datapath for Load and Store Operations (10
  minutes)
• Datapath for Branch and Jump Operations (10
  minutes)

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RTL The Branch Instruction

• beq rs, rt, imm16
• memPC Fetch the instruction from memory
• Cond lt- Rrs - Rrt Calculate the branch
  condition
• if (COND eq 0) Calculate the next
  instructions address
• PC lt- PC 4 ( SignExt(imm16) x 4 )
• else PC lt- PC 4

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Step 1) RTL To Data Path Design Data Path
Components, Overview of the
Instruction Fetch Unit

• The common RTL operations
• Fetch the Instruction memPC
• Update the program counter
• Sequential Code PC lt- PC 4
• Branch and Jump PC lt- something else

Instruction Word
32
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Datapath for Branch Operations

• beq rs, rt, imm16 We need to compare Rs and
  Rt!

Clk
Rt
Rd
Branch
RegDst
Mux
Rs
Rt
ALUctr
imm16
RegWr
5
5
5
busA
16
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
To Instruction Memory
Zero
busB
Clk
32
Mux
Extender
32
imm16
16
ALUSrc
ExtOp
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Binary Arithmetics for the Next Address

• In theory, the PC is a 32-bit byte address into
  the instruction memory
• Sequential operation PClt310gt PClt310gt 4
• Branch operation PClt310gt PClt310gt 4
  SignExtImm16 4
• The magic number 4 always comes up because
• The 32-bit PC is a byte address
• And all our instructions are 4 bytes (32 bits)
  long
• In other words
• The 2 LSBs of the 32-bit PC are always zeros
• There is no reason to have hardware to keep the 2
  LSBs
• In practice, we can simply the hardware by using
  a 30-bit PClt312gt
• Sequential operation PClt312gt PClt312gt 1
• Branch operation PClt312gt PClt312gt 1
  SignExtImm16
• In either case Instruction Memory Address
  PClt312gt concat 00

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Next Address Logic Expensive and Fast Solution

• Using a 30-bit PC
• Sequential operation PClt312gt PClt312gt 1
• Branch operation PClt312gt PClt312gt 1
  SignExtImm16
• In either case Instruction Memory Address
  PClt312gt concat 00

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Addrlt312gt
30
Addrlt10gt
00
30
Instruction Memory
30
1
32
30
SignExt
30
imm16
16
Instructionlt150gt
Instructionlt310gt
Branch
Zero
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Next Address Logic Cheap and Slow Solution

• Why is this slow?
• Cannot start the address add until Zero (output
  of ALU) is valid
• Does it matter that this is slow in the overall
  scheme of things?
• Probably not here. Critical path is the load
  operation.

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Addrlt312gt
30
Addrlt10gt
1
00
Instruction Memory
Carry In
0
30
32
SignExt
imm16
30
30
16
Instructionlt150gt
Instructionlt310gt
Branch
Zero
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RTL The Jump Instruction

• j target
• memPC Fetch the instruction from memory
• PClt312gt lt- PClt3128gt concat targetlt250gt
• Calculate the next instructions
  address

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Instruction Fetch Unit

• j target
• PClt312gt lt- PClt3129gt concat targetlt250gt

30
Addrlt312gt
30
PClt3128gt
Addrlt10gt
00
4
Target
Instruction Memory
30
Instructionlt250gt
26
30
32
30
1
Jump
Instructionlt310gt
30
SignExt
30
imm16
16
Instructionlt150gt
Branch equal
Zero
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Putting it All Together A Single Cycle Datapath

• We have everything except control signals
  (underline)

Instructionlt310gt
Branch
Instruction Fetch Unit
Jump
Rt
Rd
lt2125gt
lt1620gt
lt1115gt
lt015gt
Clk
RegDst
0
1
Mux
Imm16
Rd
Rs
Rt
Rs
Rt
ALUctr
RegWr
5
5
5
MemtoReg
busA
MemWr
Zero
Rw
Ra
Rb
busW
32
32 32-bit Registers
0
ALU
32
busB
32
0
Clk
Mux
32
Mux
32
1
WrEn
Adr
1
Data In
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp