The%20BABAR%20Silicon%20Vertex%20Tracker

1
The BABAR Silicon Vertex Tracker

• Douglas Roberts
• University of California, Santa Barbara
• BABAR Collaboration

2
Outline

• BABAR and PEP-II Design and Physics Goals
• Silicon Vertex Tracker (SVT) Design
  Considerations
• SVT Description
• Layout
• Silicon Wafers
• Upilex Fanouts
• Readout Electronics
• Front End IC (AToM Chip)
• Hybrid and Tails
• Mechanical Support
• Assembly and Testing
• Prelim. Results From Recent System Test and Beam
  Test
• Project Status

3
BABAR SVT Collaborators

• Italy
• INFN, Ferrara
• INFN, Milano
• INFN, Pavia
• INFN, Pisa
• INFN, Torino
• INFN, Trieste
• U.S.A.
• U.C., San Diego
• U.C., Santa Barbara
• U.C., Santa Cruz
• Lawrence Berkeley National Laboratory
• Stanford University
• U of Wisconsin

4
BABAR Physics Goals

• International collaboration of 530 physicists
  and engineers from 10 countries
• Primary physics goal of the BABAR experiment is
  the systematic study of CP asymmetries in the
  decays of B0 and B0 mesons.
• Reconstruct one of the B0 mesons in an exclusive
  CP-study final state
• Tag the flavor of the other B meson in the event
• Measure the relative decay time of the two B
  mesons.

B0,zCP
ee- ????(4s),?? 0.56
5
BABAR Physics Goals (cont.)

• Standard Model predicts a time-dependent CP
  asymmetry
• Time integral of Af(t) 0 at ?(4s), which makes
  a measurement of the time dependence essential
• Reason for asymmetric collider
• Good vertex determination extremely important

6
PEP-II at SLAC

• Asymmetric ee- collider
• E- 9.000GeV, E 3.109GeV
• L 3.0 x 1033 cm-2 s-1 , ultimately 1034.
• 30M BB/107s
• Time between beam crossings 4.2ns
• 0? crossing angle
• Final focus dipoles 20cm from IP
• Very little space for SVT readout electronics

7
SVT Design Considerations

• Vertexing Requirements
• Mean vertex separation of 250?m ???want single
  vertex resolution better than 80?m.
• Readily achieved with silicon strip detectors
• Acceptance
• Want as close to 4? as possible
• Magnets at 17.2?, both forward and backward
• Boost makes forward region very important
• Move most manifolds and flanges to the rear
• Coverage from 20? lt ? lt 150?.
• In center-of-mass, 0.84 gt cos?cm gt-0.95
• All electronics outside of active tracking volume
• Stand-alone tracking
• Drift chamber begins at 22.5cm, so need to
  reconstruct particles with pt lt 100MeV in SVT
  alone.
• Radiation Tolerance
• Layer 1 averages 33 krad/yr
• Non-uniform in ?
• Local max of 240 krad/yr for 6?

8
SVT Layout

• 5 Layers of double sided AC coupled silicon
  microstrip detectors
• Inner 3 layers have six modules arranged
  azimuthally around the beampipe
• Outer 2 layers have 16 and 18 modules,
  respectively.

9
SVT Layout (cont.)
Kevlar/Carbon Fiber Support Structure
Hybrid
Carbon Fiber Support Cone
Silicon
350mr
30?
Beam Pipe (1 X0)

• Each layer has strips oriented parallel (?
  strips) and perpendicular (z strips) to the beam
  line
• Total of 340 silicon wafers of 6 different types
• About 0.94m2 of silicon
• 150,000 readout channels

10
SVT Layout (cont.)
End View of BaBar Silicon Vertex Detector
11
Silicon Wafers

• 6 different wafer models
• Wafers manufactured by Micron
• Made of 300?m thick high resistivity silicon with
  a 111 orientation

12
Silicon WafersMechanical Specifications

• Physical Strip Pitch includes floating strip
  (strips not connected to readout electronics)
• Models I, II and III have ??strips on the ? side
  Models IV, V and VI have ? strips on the J side
• ? strips on wedge detector vary such that the
  ratio between width and pitch is a constant

13
Model II Wafer, ?-Side (?)
14
Model II Wafer, J-Side (z)
15
Model VI Wafer (wedge),J-Side (?)
16
Summary of Measured Wafer Parameters

• Quantity
• Rbias
• Vdepl
• Ibias
• CIS
• CAC
• Cback
• Rs (implant)
• Rs (metal)
• Radiation Damage

• Value
• 5 M? (varies)
• 15-40 V
• lt100nA/cm2
• 1 pF/cm
• 20-40 pF/cm
• 0.2, 0.4 pF/cm
• 27, 55 k?/cm
• 7, 13 ?/cm
• 300 nA/cm2/Mrad

Depends on model number
17
Upilex Fanouts
Layer 2 Fanouts
Z Fanout
Testing Area
? Fanout

• Provide an electrical connection between the
  metal strips on the silicon wafers and the
  front-end chip
• Gang together z strips on outer 2 layers (2
  strips read out by same electronics channel)
• Testing area allows for testing before readout
  electronics are attached

18
Upilex Details

• 50?m thick Upilex substrate
• UBE Industries Ltd, Japan.
• 4.5?m Cu layer deposited on an adhesive 150nm Cr
  layer
• Cu and Cr are etched to create circuit
• 150nm of Cr followed by 1?m Au (for wire bonding)
  are then electrolithically deposited
• Trace resistance is typ. 2?/cm
• Inter-trace capacitance 0.52pF/cm

19
Front-end IC(AToM Chip)

• Must amplify, shape and digitize input in
  parallel for all channels
• Buffer for duration of Level 1 trigger latency
• Sparsify data for readout
• High rates and small time between beam crossings
  (4.2ns) implies data acquisition, digitization,
  buffering and readout must occur simultaneously

20
Photo of Rad-Soft AToM
????????? 128 channels
21
Shaper Output

• Shaping time set to 100ns (setable to 100, 200,
  300 or 400ns)
• Charge injected via on-chip calibration circuitry

22
Time-Over-Threshold Output

• Comparison of analog ToT measured at comparator
  output and digitized ToT

23
Expected Noise Performance

• Based on full SPICE simulation
• Front-end circuit
• Detector network based on measured detector
  parameters
• Upilex fanout

24
Test Bench ResultsLayer 2 Module

• Test bench consists of prototype of full SVT
  readout system
• Silicon Upilex
• Rad-Soft AToM chip and Hybrid
• Prototype data transmission and DAQ

Threshold Scan
Decreasing Threshold
Firings/(50 events)
Threshold (DAC cnts)
Firings/(50 events)
Threshold (DAC cnts)
25
Test Bench ResultsLayer 2 Module
Measured Offsets and Gains for 2 ICs
26
Test Bench ResultsLayer 2 Module
Noise (in DAC counts) Measured from Threshold
Scan
? Side ENC???1070 e- (calc 880 e-)
J Side ENC???860 e- (calc 600 e-)
27
Hybrid

• Double sided, multi-layer, thick-film circuit
  fabricated on 1.2mm thick AlN
• 3 Different Models
• H1 (Layers 1 and 2) has 7 ICs/side
• H2 (Layer 3) has 10 ICs/side
• H3 (Layers 4 and 5) has 4 ICs on ? side, 5 on z
  side
• Connects to power and data transmission system
  via flexible multi-layer kapton/copper tail (2
  per hybrid)

28
Hybrid Pictures
Component Layout of H1 (Layers 1 and 2) with 7
ICs per side
Photograph of H3 prototype (Layers 4 and 5)
29
Mechanical SupportRibs and Foot
Layer 2 Rib and Endpiece Assembly
Exploded View of Foot Region
CF Endpiece
Kevlar/CF Ribs
Berg connector and tails
Cooling Ring
Silicon
UpilexFanouts
AToM IC
AlN Hybrid
30
Mechanical Support

• Modules mounted on brass cooling rings, which are
  mounted on carbon fiber support cones
• Forward and Backward cones held together with
  carbon fiber space frame
• Entire assembly mounted on B1 magnets (final
  focus RE dipoles)

31
Finished Space Frame
32
Module Assembly and Testing
? Side
Layer 2 Half-Module in Ringframe
fixture. Upilex testing area still attached.
z Side
33
Testing Probe

• Automated probe for testing modules before
  readout IC is attached
• Uses 256-pin probe array to contact testing area
  on Upilex fanout
• Connects to pA meter / Voltage source, LCR meter,
  single channel Q-amp

34
Attachment of Hybrid

• Upilex testing area is removed
• Hybrid is attached to Upilex
• Still utilizes same ringframe fixture

35
Module Stiffening
Gluing carbon fiber / Kevlar ribs to a Layer 2
Module
Finished Module after rib attachment(upside-down)
36
Arch Module Assembly

• Module is assembled flat
• Wafer-to-wafer gluing (except at bend)
• Upilex fanout glued to silicon
• Wirebonding and testing
• Attachment to hybrid
• Bend angles vary from 21? to 28?
• Bending operation done on three fixtures that
  simulate the positions of the support cone
  mounting buttons
• Defines rotation angle and axis
• Stiffening ribs attached after bending is
  complete.

37
Prelim. Testbeam Results

• CERN testbeam run with prototype layer 2 and
  layer 5 modules
• Just finished data taking Monday, Aug. 25
• All results are VERY PRELIMINARY
• Chip calibration not done.
• No alignment corrections made

Correlation between projected track position and
hits in the SVT module
PRELIM
38
Prelim. Testbeam Results

• Position correlation vs. angle of incident track.

PRELIM
39
Project Status

• Many mechanical parts fabricated support cones,
  space frame, ribs, endpieces...
• Silicon wafer production underway all 6 models
  perform as expected
• 60 of wafers already delivered from Micron
• System test has verified a working readout system
  with reasonable noise performance
• Final version of AToM IC has been submitted for
  rad-hard fabrication expect chips in Dec.
• First Layer 2 and Layer 5 modules have been
  constructed
• Goal for installation End of 1998