An AlgorithmArchitecture CoDesign Methodology for Wireless Digital Receivers

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An Algorithm/Architecture Co-Design Methodology
for Wireless Digital Receivers

• Ning Zhang
• Professor Robert W. Brodersen
• June 2000

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Abstract
Higher data rates, improved spectral efficiency
and greater capacity required by future wireless
systems can be achieved at the cost of increased
signal processing complexity. The successful
implementation of advanced algorithms and
dedicated hardware architectures to tackle the
demanding signal processing tasks calls for an
integrated development process. It must
effectively exploit the many interrelations
between the different levels of the design
hierarchy and efficiently bridge the gap between
system concepts and their VLSI circuit
realization. This project presents a systematic
approach to algorithm/architecture co-design
which leads to efficient implementations in terms
of both power consumption and silicon area.
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Hardware Design Methodology
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Algorithm Exploration

• System Level
• performance and implementation complexity
• Algorithm Level
• numerical and structural properties
• Arithmetic Level
• e.g., MAC/DIV/SQRT or CORDIC

Design Framework Matlab/behavioral Simulink
End-to-end simulation
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Architecture Exploration

• Granularity (G)
• fine, medium, coarse
• Parallelism (E)
• number of parallel processing elements
• Pipelining (q)
• number of pipelined stage for each element
• Flexibility
• reconfigurability and efficiency for other
  algorithms or parameter sets

Design Framework Structural Simulink
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Module Library Characterization
Example two-stage pipelined real multiplier
Critical path delay for N12-bit with V1V
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Estimation and Evaluation

• Architecture and Micro-Architecture level
• module-based approach for energy, area, and block
  level critical path delay estimations
• Post-Floor Plan and Post-Layout

Structural Simulink model
Block characterization
block level connectivity block switching activity
Hierarchical back-annotation
estimation
Verification
Post-layout measurements
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Design Example
A
.


m

• solve to minimize
• decompose A to an unitary and an upper
  triangular matrix
• get A-1 (mn)

n

• Applications
• interference suppression and diversity combining
  for multiple antenna systems
• multi-user detection for CDMA systems
• recursive least squares filters
• any algorithm requiring matrix inversion

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Generic QRD Hardware Core

• Design Parameters
• problem size (n, m)
• input sample rate
• system performance requirements

• Architectures
• 2D array
• 1D array (systolic and non-systolic)
• mapping and scheduling
• application-specific processor

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Hardware Implementation Comparisons
Power vs. Area for Different Hardware
Architectures

• Input sample rate of 1MHz per antenna, nm4 and
  nm12
• 0.8nJ/sample for n4 and 3nJ/sample for n12
• 40mJ/sample for n4 at 5kHz sample rate on
  TMS320C6x