An AlgorithmArchitecture CoDesign Methodology for Wireless Digital Receivers

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An Algorithm/Architecture Co-Design Methodology
for Wireless Digital Receivers

• Ning Zhang
• Bob Brodersen
• BWRC Winter Retreat, January 2000

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Wireless Communication System Trend

• Increasing demands
• High capacity
• High data rate
• with constraints
• Portability
• low energy consumption
• small form factor
• Fast time-to-market

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The Gap Between Reality and Theory
Commercial Systems (Proxim WLAN)
New Theoretical Results (Lucent V-BLAST)
Spectral Efficiency
Single-user 1-2 bps/Hz Multi-user 0.3 bps/Hz
12-40 bps/Hz
Implementation
1/10 of real-time, 650 Kbps 4 TMS32C40 DSP 7 W
1.6 Mbps 750 mW(includes analog)
Lower Power High Performance at high data rate
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Problem Statement

• How to facilitate low power digital
  implementation of high performance wireless
  communication algorithms?

Algorithm
Establish an algorithm/architecture co-design
methodology that enables efficient and effective
algorithm and architecture explorations.
Architecture
Digital Signal Processor
Dedicated Hardware
Reconfigurable Hardware
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Methodology Outline
Algorithm
Algorithm Characteristic Evaluation
Architecture
Digital Signal Processor
Dedicated Hardware
Reconfigurable Hardware
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Algorithm Evaluation
Performance and Implementation Complexity

• Theoretical capacity
• Algorithm performance
• e.g., convergence speed of adaptive algorithm
• Operation count
• Operation breakdown
• e.g., MULT, DIV, SQRT, ALU and MEM
• Sensitivity to analog circuit nonidealities
• Numerical robustness with finite precision
• Structure
• e.g., locality, regularity and concurrency

Performance
Implementation Complexity
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Methodology Outline
Algorithm
Architectural Implementation Estimation
Architecture
Digital Signal Processor
Dedicated Hardware
Reconfigurable Hardware
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Architectural Implementation Estimation

• Digital Signal Processor
• Kernel benchmark approach
• Start from existing architectures
• compiled assembly codes instruction level power
  characterizations
• Evaluate relative improvements for extensions of
  architectures
• Retargetable estimation Ghazal
• Reconfigurable Hardware
• Pleiades Wan
• Stream-based dataflow architecture Kienhuis
• Dedicated Hardware

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Low Power Design Techniques

• Identify and Estimate Potential Improvements
• Accumulate Design Knowledge

• Algorithm
• Reduce operation complexity
• Optimize computation structure
• Architecture
• Optimize fundamental components
• Reduce overhead components

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Methodology Outline
Algorithm
Fast and Predictable Implementation Path
Architecture
Digital Signal Processor
Dedicated Hardware
Reconfigurable Hardware
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Front-End Design for Dedicated Hardware
Fast and Predictable Implementation

• Use block diagram based algorithm specification

• Preserve algorithm structure to establish
  connections between algorithm, architecture and
  physical levels

increase predictability and shorten feedback loop

• Design at high level by reusing building blocks
  

increase productivity
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Module Based Approach
Algorithm
Recommendation for Modifications and
Transformations
Pre-Characterized Module Library with PDA Models
Architecture
Data Flow (construct with parameterized modules)
Control Flow
Estimation and Evaluation
(synthesize to standard cells)

(generate C code)
Netlist and Floor Plan of Macro Modules
Standard Cells
Implementation on Processor
Physical Design Information
Back-end Design flow
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Design Example
A
.


m

• solve to minimize
• decompose A to an unitary and an upper
  triangular matrix
• get A-1 (mn)

n

• Applications
• interference suppression and diversity combining
  for multiple antenna systems
• multi-user detection for CDMA systems
• recursive least squares filters
• any algorithm requiring matrix inversion

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Hardware Design Methodology

• Design Space Exploration
• System level
• performance and implementation complexity
• Algorithm level
• numerical and structural properties
• Architecture level
• parallel and pipeline schemes (speed/area/energy)
• Arithmetic level
• MAC/DIV/SQRT or CORDIC
• Design Framework
• High level modeling and estimation
• Optimizations across all levels
• System/Hardware codesign