Physical Design and Synthesis Li-Rong Zheng Professor of Media Electronics, KTH [e-mail]

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Physical Design and SynthesisLi-Rong Zheng
Professor of Media Electronics,
KTHlirong_at_imit.kth.se
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OUTLINE

• Introduction
• Floorplanning and placement
• Routing
• Elmore Delay
• Clock distribution and power distribution
• Summary

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Navigation ASIC Design in DSM Technology
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Some last synthesis steps...

• Partition your design
• Save design in a suitable net list format
• Insert scan-chains
• Insert pads
• Insert boundary scan and JTAG
• Do place and route
• Yet need some special circuits design
  analog/RF, I/O and communication schemes, clock
  distribution, power distribution etc

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Physical Compiler Based Design Flow
Source Advanced ASIC Chip Synthesis. 2nd Ed.
Himanshu Bhatnagar. Kluwer Academic Publishers
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Place Route Steps
Logic Design
Gate Netlist
Place
Noise Analysis Timing Analysis
Scan-FF insertion
Clock Tree Routing
SDF SPEF
Route
DRC Check
RC Extraction
Back annotate and design iteration
LVS Check
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Floorplanning...
Standard cell area
Horizontal channel
Macroblock (IP)
Vertical channel
Clock spine

• Goal Calculate the sizes of all blocks and
  assign them locations
• Objectives keep the highly connected blocks
  physically close to each other

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Pad Limitations...
Pad limited ASIC Core limited ASIC
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Cope with Pad Limitations
Vdd
Vss
I/O Pads
Vdd Vss for core
Pad limited ASIC Core limited ASIC
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I/O Pad with ESD Protection
Diode
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Power and Clock Planning

• Power and GND
• Use separate metal layers for Power and GND
• Global power/GND in top metal layers
• Clock
• Use separate metal layers for clock routing
• Minimize Clock skew

FO3
Ci1
e
Ci
C1
C2
C3
Load ratio for fastest switching
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Advanced On-Chip Power Distribution Schemes
Solid Planes (large decap, many vias)
Double Layer Mesh (with high speed signal
distribution)
Single Layer Grid
Distributed at top-most metal layers (thicker,
low R metals)
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I/Os and Bonding Pads
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Placement Goals and Objectives

• Guarantee that the routing algorithm can complete
  the routing step
• Minimize the critical net delays
• Make the chip as dense as possible
• Minimize power dissipation
• Minimize crosstalk between signals

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Routing steps

• Global routing
• Detailed routing
• Special routing
• Circuit extraction and DRC

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Global Routing objectives

• Minimize the total interconnect length
• Maximize the probability that the detailed router
  can complete the routing
• Minimize the critical path delay

Network of PLAs, 4 layers OTC
River PLA, 2 layers no additional routing
Standard cell, 3 layers OTC
Standard cell, 2 layers channel routing
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Wiring Hierarchy
Passivation
Number of Nets (Log Scale)
Dielectric
Etch stop layer
Dielectric diffusion barrier
Copper conductor with metal barrier liner
Global
Local
Intermediate
Pre-metal dielectric
Tungsten contact plug
Source SIA Roadmap 1999
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Wire delay estimation
Diffused signal propagation Delay L2
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Elmore delay model
t4R14C1R24C2R34C3R44C4
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Elmore delay (ctd.)
t4R14C1R24C2R34C3R44C4
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Elmore delay (ctd.)

• Use the resistance that the nodes has in common
• Use the wire segment lengths to calculate the
  capacitances

R14RpdR1 R24RpdR1 (NB!!!) R34RpdR1R3 R44
RpdR1R3R4
t4R14C1R24C2R34C3R44C4
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Detailed Routing

• Design rules - wire pitch
• Via-to-Via
• Via-to-line
• line-to-line

3l
6l
7l
6.5l
4l
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Detailed routing objectives

• Minimize
• Total interconnect length and area
• The number of layer changes ( of vias)
• The delay of the critical path

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Special Routing

• Clock Tree Routing
• Minimize Skew and reduce Jitter
• Jitter caused by power supply noise
• Power Routing
• Calculate wire widths to carry the current
• Depends on MTTF (Mean Time To Failure)
• MTTF AJ-2exp(-E/kT) gt 10 years

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Setup- and Hold-times
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Clock skew factors

• Clock skew is increased by
• number of buffers in the path
• differences in length from clock source to end
  nodes
• Clock skew is decreased by
• wider buffers in the path
• phase compensators (PLLs, DLLs)

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Retiming Local Clock Skew
What is the critical path of this circuit?
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Synchronization is the goal

• The purpose of the clock is to provide
• a way to synchronize the latches in the chip with
  the external world
• a way to synchronize the latches in the chip with
  each other

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Classes of Synchronization

• There are five classes of synchronization
• Synchronous
• Mesochronous
• Plesiochronous
• Periodic
• Asynchronous

(More details in 2B1428 Advanced VLSI Design )
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General Clock Distribution Tree
PLL
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Symmetric Clock Distribution Networks
a) H-tree b) X-tree
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Common Buffered Trees
a) Tapered H-tree b) Mesh
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DEC Alpha Clock Distribution
21064 21264
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PVT variations

• Process variations
• Insulator thickness differences
• Voltage variations
• Voltage drops because power lines are resistive
  and have to support the peak currents
• Temperature variations
• Local hot-spots have higher temperatures which
  makes the chip slower

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Clock skew and jitter
PVT (Process Voltage Temperature) variations
BC (Fast) Corner
PVT Gradient
tskewtslow-tfast
WC (Slow) Corner
Die size (D)
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Switching Activity
P
Peak power
Average power
t
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By-pass capacitance prevents rail voltage from
jumping
VR
GATE
I
GND
a) active gate b) passive gate c) by-pass
capacitance
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Power Distribution and Decoupling Strategy
389 Signal - 198 VDD/VSS Pins
389 Signal Bondwires
395 VDD/VSS Bondwires
320 VDD/VSS Bondwires
WACC
Microprocessor
Heat Slug
Example EV6 34nF of effective switching
capacitance 320nF of de-coupling capacitance --
not enough!
(More details in 2B1428 Advanced VLSI Design )
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Summary

• Floorplanning placement
• Routing, DRC and LVS check
• Clock-tree routing and power distribution
• Post-layout verifications
• If you are lucky, youll probably get a working
  chip after some logic-physical design iterations
• More advanced design issues (lower power, higher
  performance, such as advanced m-processors and
  communication circuits design), continue in
  course 2B1428.

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Follow up Course 1 2B1428 Advanced VLSI Design

• Focus on Advanced System and Circuits Level
  Design for
• Low power high-performance on-chip
  communications
• Current-mode vs voltage mode driving, LVDS,
  bi-directional signaling, receivers,
  equalization, x-talk and noise budget etc
• Timing and synchronization techniques
• Different timing circuits, PLL, DLL,
  synchronizers (synchronous, mesochronous
  plesiochronous, periodic, asynchronous design)
  etc
• Power and clock distribution
• Power supply network, decoupling allocation,
  multiple supply distribution and isolation, clock
  generators, advanced clock distribution schemes
  etc

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Examples
Bundled Closed-Loop Timing
Current-mode driving circuits
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Follow up Course 2 2B1450 Electronic System
Packaging (mixed-signal system design)
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2B1450- with focus on system and product level
design of electronic systems