L2 Goals - PowerPoint PPT Presentation

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L2 Goals

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ISOLIST, RECES, extra TRACKlist, more Alfas... Install new XTRP data boards (mid Oct) ... L1, CLIST, XTRPlist, SVTlist, 4 Alfas (RECES, ISOLIST) L1A rate ~ 25 KHz ... – PowerPoint PPT presentation

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Title: L2 Goals


1
L2 Goals
? done
  • Near term (by Oct 8)
  • Demonstrate cutting on jets and SVT tracks
  • Intermediate term (Nov 17 to end of 2001)
  • Come back from shutdown cutting on jets and SVT
    tracks
  • Commission SVT trigger operation
  • Commission electron trigger
  • Far term (early 2002)
  • Establish stable L2 operation
  • Commission remaining interface boards (RECES,
    ISOLIST, MUON) to cut on
  • Electrons
  • Photons
  • Muons

work in progress
2
L2 near term plan(by Oct 8)
? done
  • Cutting on jets
  • Reliable CLIST
  • Reliable L1 board
  • Sync errors lt 10-6 L1As
  • Automated HRR
  • Cutting on SVT tracks
  • Solve XTRP problem
  • Reliable SVTlist
  • Alfa code
  • Cutting on electrons
  • Solve XTRP problem
  • Reliable XTRPlistCLIST
  • Solve CLIST eta-phi errors?
  • Alfa code
  • Also
  • Magic Bus tests design new backplane
  • AC termination

SVT parallel path (backup)
  • 2a. SVT to TS direct path
  • Kludge card/cable
  • Firmware
  • RC work?

? done
? done
  • not finished

?
?
?
? done Dec 1
?
? not done
? done
3
L2 plans for shutdown(Oct 8 to Nov 17)
? in progress
  • Improve documentation
  • Protocols
  • FPGA firmware
  • Etc.
  • Prepare tests of MB arbitration (Oct 8-15)
  • Remove delays from firmware
  • Test different board configurations and
    characterize collision problem
  • Install new MB (Oct 15-22)
  • Repeat tests (see above) and compare
  • Test at maximum bus load
  • ISOLIST, RECES, extra TRACKlist, more Alfas
  • Install new XTRP data boards (mid Oct)
  • Full phi coverage
  • At a lower priority (in this time frame)
  • Test multiple Alfa operation
  • Tests of ISOLIST and RECES

? done
? Installed on Dec 4
? done
? done
4
L2 milestones
? done
  • Sept 19? New Magic Bus review
  • Oct 25 New Magic Bus working with
  • L1, CLIST, XTRPlist, SVTlist, 1 Alfa
  • Artificial delays removed from firmware
  • L1A rate 10KHz
  • Deadtime from errors lt 2
  • Data error rate lt 10-7
  • Jan 1 New Magic Bus working with
  • L1, CLIST, XTRPlist, SVTlist, 4 Alfas (RECES,
    ISOLIST)
  • L1A rate 25 KHz
  • Deadtime from errors lt 2
  • Data error rate lt 10-7

old
?
?
?
20KHz
?
?
5
What if we fail the Oct 25 milestone?
  • Implement a modified/simplified arbitration
    scheme that will allow us to trigger on jets and
    SVT shortly after we come up on Nov 17
  • We need a very precise plan and maybe some
    preparatory work by Oct 25, so that we are
    confident it can be implemented by Nov 17
  • Brainstorming of ideas must start now
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