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1
??-220

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2
Contacts

• Mailing List
• mail majordomo subscribe hy220-list
• ??????
• ?????? ?a?????? vlahos_at_csd.uoc.gr
• ???e????a?????? G?????? mihelog_at_csd.uoc.gr
• ?a????t??
• ?a???e?d?? ????ß?? jacob_at_csd.uoc.gr

3
Website

• Website
• http//www.csd.uoc.gr/hy220
• http//www.csd.uoc.gr/hy220/lectures
• http//www.csd.uoc.gr/hy220/lab_ex.html

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Grading

• ???ast???a 30
• 3 ???ast???a
• ????d?? 20
• ?p???e?t???
• ?e????? 50
• ??s? ?e????? 3.5

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Who should attend this class ?

• F??t?t?? p??
• ?e? ????????? H/W ?a? ?????? ?a ap??t?s??? ap???
  ?e????? ???se??.
• T????? ??a e?sa?????? µ???µa p??? ap?
  p????-??µ??e? e?e?d??e?µ??e? ???se??.
• T????? ?a ?????? µ??a????? ?p?????st?? ?a
  s?ed?????? ?a? ?a ?atas?e?????? ????????-µ??a
  ?????µata.

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Lecture Plan (1)

• Verilog 2.5 weeks
• Basics, Advanced, Examples
• System Design Flow 2 weeks
• VLSI, FPGAs, CAD tools, System on Chip
• Finite State Machines 1.5 weeks
• Sequential Logic
• Register, Latches

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Lecture Plan (2)

• 5. Memory 2 weeks
• SRAM, DRAM, Decoder, FIFO, CAM
• 6. Busses 1 weeks
• Protocols, Master/Slave, Synch/Asynch,
  MotherBoard
• Clock 1 weeks
• Clock, Skew, Clock Trees, Asynchronous design
• Schedulers 1 weeks
• Register, Latches