Figure 10'1 Truth table and schematic diagram for a binary halfadder'

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1
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10.1 Simple Adders Half-adder
Figure 10.1 Truth table and schematic diagram
for a binary half-adder.
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Full-adder
Figure 10.2 Truth table and schematic diagram
for a binary full adder.
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AddersHalf adder add two digits without
considering carry in.
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Full adder add two digits and carry in.
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Figure 10.3 Full adder implemented with two
half-adders, by means of two 4-input
multiplexers, and as two-level gate network.
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Ripple-carry n-bit full-adder
Figure 10.4 Ripple-carry binary adder with
32-bit inputs and output.
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Carry Propagation Networks
Figure 10.5 The main part of an adder is the
carry network. The rest is just a set of gates to
produce the g and p signals and the sum bits.
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Figure 10.6 The carry propagation network of a
ripple-carry adder.
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Speed up of carry propagation Provide a skip
paths in a ripple-carry network.
Carry equation remains the same for c4j, c4j1,
c4j2, c4j3, but c4j4 different.
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Figure 10.8 Driving analogy for carry
propagation in adders with skip paths. Taking the
freeway allows a driver who wants to travel a
long distance to avoid excessive delays at many
traffic lights.
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10.3 Counting and Incrementation Necessity e.g.,
set a register to a value x, and repeatedly add a
constant a. sequence values, x, x1a, x2a Full
adder additional circuit
Figure 10.9 Schematic diagram of an
initializable synchronous counter.
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Incrementer a 1 By setting cin1, y0,
therefore,
Figure 10.10 Carry propagation network and sum
logic for an incrementer.
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10.4 Design of Fast Adder

• Brent-Kung carry lookahead network
• a, b stands for (ga,b, pa,b)
• Carry operator combines the generate and
  propagate signals for two adjacent blocki1,j
  and h,i of digital positions into respective
  signals for wider block h,j.

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G01 G11 or ( P11 and G00 ) P01 P11 and P00
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8-input Brent-Kung network composed of a 4-input
Brent-kung network two rows of carry operators.
Figure 10.12 Brent-Kung lookahead carry network
for an 8-digit adder, with only its top and
bottom rows of carry operators shown.
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Blocks needed in the design of carry-lookahead
adders with four-way grouping of bits.
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Carry-select adder K-bit adder one (k/2)-bit
adder in lower half two (k/2)-bit adders in
the upper half.
Figure 10.14 Carry-select addition principle.
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16 bit Brent-Kung Carry Lookahead Network
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16 bit Sklansky adder
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10.5 Logic and Shift Operations
Figure 10.15 Multiplexer-based logical shifting
unit.
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Shift instruction in MiniMIPS shift right
arithmetic and shift right arithmetic
variable sra t0, s1, 2 set
t0 to (1) right-shifted by 2 srav t0, s1,
0 set t0 to (1) right-shifted by (s0)
Figure 10.16 The two arithmetic shift
instructions of MiniMIPS.
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Figure 10.17 Multistage shifting in a barrel
shifter.
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Figure 10.18 A 4 8 block of a black-and-white
image represented as a 32-bit word.
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10.6 Multifunction ALU

• ALU adder AND, OR, XOR, NOR gates
• Example in Fig.10.19
• (1) Arithmetic operation F1F010
• (i) add/Sub 0 xy
• (ii) add/Sub 1 x-y xy1
• (2) Logic operation F1F011, AND, OR, XOR, NOR
• (3) Shifter

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Figure 10.19 A multifunction ALU with 8 control
signals (2 for function class, 1 arithmetic, 3
shift, 2 logic) specifying the operation.