Timing Analysis for Sensor Network Nodes of the Atmega Processor Family

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Timing Analysis for Sensor Network Nodes of the
Atmega Processor Family

• Sibin Mohan, Frank Mueller
• (North Carolina State University)
• David Whalley (Florida State University)
• Christopher Healy (Furman University)

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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Introduction

• Real-time systems theory
• Schedulability of task sets
• Task defined by ?, p, e, d
• where, ? phase
• p period
• e worst-case execution time
• d deadline

Statically determine above parameters.
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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Timing Analysis

• Dynamic Timing Analysis
• Experimental/trace-driven
• Cannot guarantee safety
• Worst-case input sets required
• Architectural complexity
• the alternative Static Timing Analysis

Wegener, Mueller in Real-Time Systems, Nov
2001.
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Static Timing Analysis

• Static analysis of code segments for WCET
• Guaranteed upper bounds on task computation
• Model traversal of all possible execution paths
• Timing independent of traces/program values.

• Loop Bodies
• Timing obtained by fixed point approach

• Behavior of architectural components
• captured as execution paths are traversed

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Static Timing Analysis (contd.)
Path
Path
Path
Loop
Loop
Function
Function
Task
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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Timing Analysis Framework
Cache Configuration
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Timing Analysis Framework (contd.)

• Timing Analyzer uses
• Control flow information
• Caching categorizations
• Pipeline description

• Pipeline Simulator considers
• Structural and data hazards
• Cache misses
• Branch Predictions static prediction

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Timing Analysis Framework (contd.)

• Path Analysis
• Selects longest path
• Fixed point algorithm on alternate paths
• Safely bound iterations of a loop

• Timing Analysis tree constructed
• Each path, loop and function

• Provides mechanism to time scopes
• sub-tasks

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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Atmel Architecture

• Atmega103 and Atmega128
• Low-power, 8-bit CMOS microcontrollers
• AVR enhanced RISC architecture
• Harvard architecture
• Separate memories/buses for program and data

• Two-stage pipeline
• Instruction fetch
• Execute

• No instruction or data caches.

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Atmega AVR Instruction Set

• 16 or 32 bits wide
• Only integer operations
• Floating point operations emulated by compiler
  routines.

Instructions Function Cycles
rcall, icall, call Subroutine calls 3 / 4
eicall Extended indirect call 4
ret, reti Subroutine returns 4 / 5
cpse Compare, skip if equal 1 / 2 / 3
sbrc, sbrs, sbic, sbis Skip if bit is set/clear 1 / 2 / 3
brxy Conditional branches 1 / 2
lpm, elpm Load program memory 3

• All other instructions 1 or 2 cycles

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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Adapting to Architectural Features

• Variable-cycle instructions
• Number of cycles depends on context
• Accurate Pipeline Modeling
• Overlap across adjacent loop iterations

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Variable-cycle Instructions

• Consider a branch instruction
• Traditional WCET analysis
• Overestimation

• Modify Path Merging Code

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Accurate Pipeline Modeling

• Adjacent loop iterations
• Errors accumulate over loop iterations

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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Timing of NesC code

• Various NesC structures
• Commands, Events, Tasks, etc.
• Commands ? synchronous code
• Timing performed for commands.
• Intermediate C code examined
• information ? loop bounds
• Events ? asynchronous code
• Event body timed separately

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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Experimental Setup

• Three-tiered set of experiments

• Mica Berkeley Sensor Motes
• AVRStudio
• cycle-accurate simulator
• from manufacturers of Atmel
• WCET bounds
• Timing Analyzer

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Experimental Setup (contd.)

• Measurement Methods
• Berkeley Motes hardware interrupts, counters
• AVRStudio breakpoints in simulator
• Timing Analyzer
• WCET bounds for loops, functions, tasks

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Benchmarks

• C-Lab embedded benchmark suite
• Five integer benchmarks

Benchmark Function
Sum array Sum and count of positive and negative integers in array
Fibcall Generate the nth Fibonacci number
Insert sort Implementation of insertion sort
Matrix mult Matrix multiplication
Bubble sort Implementation of bubble sort

• NesC benchmarks

Benchmark Function
ArraySum Sum of numbers in an array
RC5.encrypt RC5 Encryption
RC5.decrypt RC5 Decryption
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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Results

• C-Lab benchmarks results

Benchmark Motes Simulator Simulator Timing Analyzer Timing Analyzer Timing Analyzer Timing Analyzer Timing Analyzer Timing Analyzer
Cycles Cycles Ratio Initial Cycles Ratio Pipeline fix Ratio Var. Ins. fix Ratio
Sum array 141, 500 141,597 0.99 161,498 1.14 141,500 1.00 141,600 1.00
Fibcall 145 140 0.96 258 1.78 202 1.39 146 1.01
Insert sort 1,613 1,606 0.99 1,978 1.23 1,880 1.17 1,861 1.15
Matrix mult 1,845 1,842 0.99 2,318 1.26 2070 1.12 1,878 1.01
Bubble Sort 3,628,239 3,628,239 1.00 3,900,998 1.08 3,650,000 1.01 3,776,518 1.04
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Results (contd.)

• NesC benchmarks results

Benchmark Motes Simulator Simulator Timing Analyzer Timing Analyzer Timing Analyzer Timing Analyzer Timing Analyzer Timing Analyzer
Cycles Cycles Ratio Initial Cycles Ratio Pipeline fix Ratio Var. Ins. fix Ratio
Array Sum 81 92 1.14 105 1.30 87 1.07 88 1.09
RC5.encrypt 15,951 15,946 1.00 17,958 1.13 16,088 1.00 16,088 1.00
RC5.decrypt 15,855 15,850 1.00 1,982 1.13 16,112 1.01 16,122 1.01
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Results (contd.)

• Scalability of Timing Analyzer
• Varying loop/inputs sizes
• WCET bounds scale up well
• Constant difference maintained

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Outline

• Introduction
• Timing analysis
• Static timing analysis framework
• Atmel architecture
• Adapting to architectural features
• Timing for NesC code
• Experimental setup benchmarks
• Results
• Conclusions.

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Conclusions

• Timing Analyzer for Atmel
• Timing Analysis for NesC
• first known tool for this purpose
• Safe and tight WCET bounds
• Never under-estimates WCET
• Solutions for unique problems
• Variable-cycle instructions
• Accurate pipeline modeling for loop iterations

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Thank You !Questions ???