A%203-V%20Fully%20Differential%20Distributed%20Limiting%20Driver%20for%2040%20Gb/s%20Optical%20Transmission%20Systems

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A 3-V Fully Differential Distributed Limiting
Driver for 40 Gb/s Optical Transmission Systems
D.S. McPherson, F. Pera, M. Tazlauanu, S.P.
Voinigescu Quake Technologies, Inc. Ottawa, ON,
K2K 2T8, Canada
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Outline

• Overview
• Device modeling
• Circuit design and features
• Measurement results
• Summary

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Design overview

• Fully differential
• AC coupled at the input
• DC coupled to the modulator
• Based on a 0.15 mm GaAs PHEMT technology
• Uses double source follower inverter gain stages
• Output drive stage is distributed
• Operates in limiting mode
• Includes additional control features

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Scalable PHEMT model extraction

• An accurate scalable model is essential for this
  design
• It must capture the transistors characteristics
  over the entire bias range
• For the present design, the Agilent EEsof
  Scalable Nonlinear HEMT model was used
• The model is implemented in Agilent EEsof EDAs
  Advanced Design System

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Extraction geometries and conditions
Gate geometries 1 x 10 mm2, 1 x 20 mm2, 1 x 40 mm2 2 x 40 mm2, 2 x 60 mm2
Vgs -0.9 V 0.5 V
Vds 0 V 5.0 V
Frequency 45 MHz 50 GHz
Temperature 18 C and 100 C
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Transfer characteristics
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fT versus geometry and temperature
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Driver specifications
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Circuit schematic
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Gain block architecture
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Distributed output stage
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Control function implementation
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Chip microphotograph

• Fabricated by Fujitsu Quantum Devices Limited
• 0.15 mm AlGaAs/InGaAs PHEMT process
• Substrate height of 28 mm
• Single-metal layer with underpasses
• Through-wafer vias for grounding
• Schottky diodes
• Epitaxial resistors

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Setup for on-wafer eye measurements
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Bandwidth of measurement setup
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40 Gb/s eye-diagram (test setup)

• Tr 12.7 ps
• Tf 11.9 ps
• Tj 6.7 ps

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Nominal eye-diagrams

• Output swing of 3.0 Vp-p per side
• Rise/fall times are 10.9/11.4 ps
• Jitter is 8.6 ps (peak to peak)

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Control features applied at 40 Gb/s
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Control features applied at 40 Gb/s
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Summary

• A full featured 3-V 40 Gb/s modulator driver has
  been designed and fabricated using a GaAs PHEMT
  process
• Limitations associated with the technology,
  particularly its low fT, can be overcome in
  design
• The design is very challenging because it
  involves a complex set of trade-offs
• The result is a unique and robust circuit that
  exhibits excellent yield and performance

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Acknowledgment

• The authors would like to thank Fujitsu Quantum
  Devices Limited for fabricating the die
• They would also like to express their gratitude
  to Quake colleagues H. Tran and D. Viorel for
  their valuable contributions