IBM Research GmbH Zurich Research Laboratory Rschlikon, Switzerland

1
IBM Research GmbHZurich Research
LaboratoryRüschlikon, Switzerland
Design of Source-Series-Terminated (SST)
Transmitters with T-coils

• Marcel Kossel, Christian Menolfi, Matthias
  Brändli, Peter Buchmann, Thomas Morf, Thomas
  Toifl, Martin Schmatz
• Sept 23, 2009

2
Outline

• Basic SST architecture
• Impedance tuning and equalization concepts
• Design example of high swing SST transmitter
• Impedance matching T-coil
• Measured results
• Performance summary

3
Concept of source-series-termination

• Advantages of SST over CML
• Many different termination voltages
• can be supported together with a
• higher signal swing
• No static power consumption due to
• CMOS-oriented design style

4
Key design targets

• Coarse and fine impedance control
• Independent adjustment of equalization settings
  and impedance tuning
• Support of different dc supply levels
• Slew rate control
• Skew control

High-level schematic of implemented driver circuit
5
Impedance tuning
Slice approach Pro easily scalable (e.g. DDR
applications) Con only suitable for coarse tuning
Header and footer devices Pro suitable for fine
tuning Con reduced voltage headroom
6
Equalization (1)

• Objective
• Z independent of equalization

• De-emphasis

• Impedance
• Z determined by K out of N

7
Equalization (2)

• Independent adjustment of equalization and
  impedance tuning
• ? Each slice contains a complete set of
  pre-emphasis weights.

8
Equalization (3)

• Decomposition into minimum number of
  equalization weights.
• ? Weight allocator allows change of FFE
  configuration.

9
Thin-oxide (50 nm ) pre-driver

• 5-bit 2-tap equalization with complementary tap
  weights
• ? main tap weight1-post cursor weight
• Duty-cycle restoring clock path.

10
Thick-oxide (100 nm ) output stages

• Each output stage slice contains a complete set
  of equalization
• weights
• ? equalization and impedance tuning are
  orthogonal.
• Pre-emphasis has 5-bit amplitude resolution.

11
Clock path
Output data DCD _at_ 5.0Gb/s

• Capacitive source-degenerated
• clock buffer and CML-to-CMOS
• converter help restore duty
• cycle (5x improvement).

Clock duty-cycle distortion _at_ 2.5GHz
12
T-coil for wideband impedance matching
40um
40um
TCRBEOL0.3/oC TCRpres0.2/oC

• T-coil cancels ESD parasitics
• Resistance ratio Rpoly/RFET1.68
• EM simulated with HFSS

13
Symmetrical T-coil with varying capacitance
distribution

• S11 and S21 degrade as Ce/Ct
• becomes smaller if the T-coil is
• symmetric
• ? Asymmetric T-coil is required
• with LagtLb.
• Lb carries high ESD current.

14
Return and insertion loss improvement owing to
T-coil

• Tx without T-coil
• Tx with T-coil
• Package only
• Package attached to Tx with T-coil
• Package attached to Tx w/o T-coil

FCPBGA package with 16 mm package conductor
length and 3 mm board microstrip.
Return loss improvement due to T-coil S11lt-16
dB over 10 GHz bandwidth
15
2-channel SST Tx test chip in 65 nm bulk CMOS
technology
half-rate clock input
Ch1 outp
Ch2 outp
Ch2 outn
Ch1 outn

• Test chips with three different output
  configurations
• A no ESD no T-coil
• B with ESD no T-coil
• C with ESD with T-coil

16
Miscellaneous measurements (1)
7.5Gb/s -1.9dB de-emphasis over 3.5m cable
BER
0.5V
1E-2
TJ0.125UI DJ0.099UI RJ1.8mUI
6.0Gb/s BERT eye
1E-4
1E-6
1E-8
-0.5V
200mV/div 22.2ps/div
0.5UI
-0.5UI
S11 dB
ESD only
no ESD T-coil
w/ T-coil
5.2Gb/s PRBS-7
D24.2mV
freq. GHz
17
Miscellaneous measurements (2)
18
Performance summary