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ECE 223 LAB 1

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If blanking input is 1 display is blank. Outputs: a,b,c,d,e,f,g. 0001 = A. 0010 ... Use K-maps, don't use blanking input in maps. Have a K-map for each output ... – PowerPoint PPT presentation

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Title: ECE 223 LAB 1


1
ECE 223 LAB 1
  • Preetha Thulasiraman
  • pthulasi_at_bbcr.uwaterloo.ca
  • Winter 2007

2
What you need to do
  • Part 1 Gear Shifter System
  • Part 2 Decoder for Seven Segment Display
  • Demonstrations
  • Lab Report

3
Part 1 Gear Shifter System
  • Inputs (w, x, y, z)
  • Gear Position
  • Gear Request

4
  • Outputs
  • Enable
  • Direction
  • Enable Direction
  • 1 ? Shift gears 1 ? Shift gear up
  • 0 ? Do nothing 0 ? Shift gear down

5
Example
  • To shift from second to neutral

6
  • Design
  • A) use 2 input NAND gates
  • B) use any gates available, minimize as much as
    possible
  • Hint Use K-maps
  • Consider invalid cases
  • What happens to your design if 4th gear added
  • Implement one of your designs using TTL gates and
    speedwire
  • Simulate and test design

7
Part 2 Decoder for Seven Segment Display
  • Inputs w,x,y,z, blanking input
  • If blanking input is 1 display is blank
  • Outputs a,b,c,d,e,f,g
  • 0001 A
  • 0010 B
  • 1010 J

8
Example
  • To show letter A
  • Seven segment display is ACTIVE LOW
  • Use K-maps, dont use blanking input in maps
  • Have a K-map for each output
  • Simplify design by noticing similarities between
    and within maps

9
Help Sessions
  • For lab help sessions
  • Do most of design work BEFORE coming to the lab
  • i.e. problem analysis, K-maps, VHDL code,
    schematics must be done

10
Demo
  • Day of demo must show
  • VHDL code, simulation and schematics for both
    parts
  • Hardware must work to receive full points
  • VHDL code must work
  • Answer questions about your implementation
  • Print out and bring submission form

11
Final Report
  • Lab submission form (front page)
  • Include
  • Problem definition/specification
  • Circuit design information
  • Final circuit schematic
  • Simulation command files
  • Simulation waveforms
  • VHDL code
  • Show all intermediate designs (i.e. K-maps, truth
    tables etc.)
  • Discuss debugging strategies, problems
    encountered, provide an analysis of your work
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