SelfCompensating Design for Focus Variation

1
Self-Compensating Design for Focus Variation

• Puneet Gupta1, Andrew B. Kahng1,
• Youngmin Kim2, Dennis Sylvester2
• 1 Blaze DFM Inc., Sunnyvale CA
• 2 EECS Department, University of Michigan, Ann
  Arbor

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Outline

• Introduction
• Compensating Focus Variation
• Linewidth Variation with Defocus
• Experiments and Results
• Conclusion and Future Works

3
Introduction

• Within-die process variation has become one of
  the most important considerations in
  sub-wavelength regime.
• Across chip linewidth variation (ACLV) control is
  critical to the timing and functionality of a
  design
• Exploit of various RETs (Resolution Enhancement
  Techniques)
• SRAF, OPC, PSM, and etc
• Components of variation
• Intrinsic variation (fabrication stage)
• Random
• Systematic
• Dynamic variation (circuit operation)
• Motivations
• Focus is one of the major source of Leff
  variation
• Traditional corner-case timing is very
  pessimistic in worst-case focus impact
• Layout pitch and focus have very systematic
  interactions (e.g. Bossung plots)
• Systematic through-pitch and through-focus
  variation can reduce timing uncertainty by up to
  40 (P.Gupta, H.Fook-Luen, Proc.DAC, 2004)

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Compensating Focus Variation

• Reducing systematic variation by OPC and AFs, but
  not completely.
• Key Idea Isolated and dense lines retaining
  opposite behavior under varying defocus ?
  compensating for systematic variation in the
  design itself.
• Compensation
• Self-compensated cell layout compensation
  within-cell (e.g. one device iso and the other
  dense)
• Self-compensated physical design compensation
  across cells (e.g. G1?G2, G1 iso gate, G2
  dense gate)

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Self-Compensating Design Flow

• Litho. Simulation and construction of CD look-up
  table (LUT) gives the Leff at different spacing
  (S) and focus (F) values
• CD f ( Left Space, Right Space, Focus)
• Library generation
• 21 cells, 4 variants of each cell (original,
  iso, dense, and self-compensated cells)
• Self-compensating design
• Self-compensated cells
• Optimization (self-compensated physical design)
• Dense iso design
• Original iso design
• Optimization of delay versus area
  sensitivity-based approach to minimize area
  penalty while instantiating iso counterparts of
  dense cells in the circuit to meet timing
  constraints.

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Linewidth Variation with Defocus
Parameters
13
11

• 3 different range of space (criteria 4nm CD
  variation from nominal)
• Dense 180nm 260nm
• Self-compensated 280nm 360nm
• Iso 360nm 400nm
• (Note that 1st SB insertion point is at 420nm
  spacing)
• In most-iso (i.e. 400nm), linewidth decreases
  11 from nominal at 0.4um defocus, while in
  most-dense (i.e. 180nm), linewidth increases
  13 from nominal

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Edge Devices
Case1 no neighboring devices on either side
Case2 only one neighboring device

• The distance from edge devices to the cell
  boundary for all cells is over 600nm ? the
  distance of two neighboring poly lines gt 1.2um
• In case1, linewidth is insensitive to focus after
  two SBs are inserted (i.e. space gt 700nm) ?
  self-compensated
• In case2, 180nm case behave like dense but,
  380nm case behave like self-compensated

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Sample Cell Layout (NAND2x6)
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Experiments and Results

• Worst-case path delay of selected ISCAS85
  benchmarks with iso/dense/self-compensated
  libraries at 0.0 and 0.4um defocus level
• In average, dense cells at 0.4um defocus give 15
  slower timing and iso cells at 0.4um defocus give
  9 faster timing than original library at 0.4um
  defocus
• Average area overhead of the different cell
  versions (3.2 for dense, 17.4 for iso, and
  10.3 for self-compensated cells)

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Optimization (Self-Compensated Physical Design)

• Sensitivity-based optimization of delay versus
  area by instantiating iso counterparts of
  dense cells

While worst_slack is negative Calculate
sensitivities of all gates in the circuit Sort
sensitivities in non-increasing order Swap the
dense version with iso cell based on the
order of sensitivities Calculate new_delay of
circuit Update worst_slack
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Optimization Results (c3540)

• Black line below 0.0 slacks implicate timing
  failure over 0.23um defocus level in original
  library.
• Self-compensated design, optimization (denseiso,
  originaliso) all satisfy the timing requirement
  throughout the defocus range

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Area Penalty of Self-Compensating Design

• 10 12 area penalty for self-compensated cell
  base design
• 6 9 area penalty for the dense iso
  optimization
• Less than 1 of area overhead in original iso
  optimization
• 32 of dense gates need to replace to meet the
  timing in dense iso, but only 11 of original
  cells need to replace in original iso
  optimization

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Distribution of Focus and Delay

• Monte-Carlo simulation with 1000 trials
• Normal distribution of focus with mean0.0um and
  3s0.4um
• C3540 benchmark circuits with require time
  2.177ns is shown
• 2 optimization strategies demonstrate appreciably
  tighter distribution than self-compensated cells
  option.

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Conclusion and Future Works

• A novel design technique to compensate for
  lithographic focus variation is proposed
• More robust design to focus variation
• Self-compensated cells
• Optimization (i.e. Dense iso, Original iso)
• Dense and iso optimization option shows 69 area
  overhead compare to 1012 in a self-compensated
  library base design. Only 1 area penalty by
  using original library and iso library
• The impact of compensating design of more
  advanced technology will be even greater (e.g.
  65nm)
• Layout generation for self-compensated, iso, and
  dense cells, and APR flow for more accurate
  timing and area analysis.
• Joint optimization in the delay/area/leakage
  space ( iso fast but leaky, dense slow but less
  leaky)

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Thank You!