????te?t????? ?p?????st??

1
??425 ????te?t????? ?p?????st?? ???????µ??e?
?e?????? Pipelining. ????ß?? ?a???e?d??
2
?pe?e??ast?? DLX
Memory Access
Write Back
Instruction Fetch
Instr. Decode Reg. Fetch
Execute Addr. Calc
MUX
Next PC
Return PC (Addr 8)
Branch?
Imm
Opcode
MUX
???µ? ??t????
Reg File
???µ? ?ed?µ????
MUX
MUX
Sign Extend
WB Data
Imm
RD
RD
RD
3
??t??es? ??t???? se se??? in order
execution. (G??st? ap? p??????µe?a µa??µata)
??????
IF
ID
MEM
WB
DIV.D F0, F2, F4
DIV0
DIV1
DIV2
RAW
bypass
ADD.D F10, F0, F8
IF
ID
EX
MEM
WB
stall
stall
??? ??????µµat??
EX
SUB.D F12, F5, F6
IF
ID
MEM
WB
stall
stall
IF
ID
MEM
WB
EX
ADD.D F11, F5, F6
?? ? d?a??es? ??e???eta? 10 ??????? DIV0, DIV1
DIV9 9 stalls ?a? 9 ?aµ???? ??????...
4
??t??es? ??t???? e?t?? se??? out of order
execution (?? ??µa p?? ?a µa? apas????se? sta
ep?µe?a µa??µata)
??????
IF
ID
MEM
WB
DIV.D F0, F2, F4
DIV0
DIV1
DIV2
more resources multiported RF
RAW
bypass
ADD.D F10, F0, F8
IF
ID
EX
MEM
WB
stall
stall
ALU exception?
??? ??????µµat??
EX
SUB.D F12, F5, F6
IF
ID
MEM
WB
structural hazard
ADD.D F11, F5, F6
IF
ID
MEM
WB
EX
stall
?? e?t???? st?????ta? ??a e?t??es? µ???? e??a?
d?a??s?µe? ?? t?µ?? t?? source registers ?a?
ef?s?? de? ?p???e? structural hazard. ???µa ?a?
a? ? d?a??es? ??e???eta? 10 ??????? ? pipeline
????? ??a 1 ????? (1 stall).
5
Instruction Level Parallelism

• Instruction Level Parallelism (ILP)
• Potential overlap among instructions
• ?a??????? ? out-of-order e?t??es? e?t????.
• ?p??tas? t?? ap??? pipelining a???te?t??????
• Loop Level Parallelism
• ??µet???e?s? ILP µeta?? e?t???? ap? d?af??et???
  ßas??? blocks.
• e.g. Iterations of a loop
• for (i1 ilt100 i) xi xi yi
• ???s??? ?a d?at?????ta?
• 1. Data flow
• ? p?a?µat??? ??? t?? t?µ?? a??µesa st?? e?t????
  p?? d?µ???????? ta ap?te??sµata ?a? t?? e?t????
  p?? ta ???s?µ?p?????. (RAW, WAW, WAR)
• 2. Exception Behavior
• ???a?? st?? se??? e?t??es?? t?? e?t???? ?a µ??
  a????e? t?? se??? t?? p?? d?µ???t????ta? ta
  exceptions ? ?a µ?? d?µ????????ta? ?a??????a
  exceptions.

6
?e?????? e??tt?s?? stalls.
CPI Ideal CPI Structural stalls RAW stalls
WAR stalls WAW stalls Control
stalls St? 1? pa??de??µa (in order execution)
e??aµe 2 RAW stalls ?a? ?a???a ???? stall. St? 2?
pa??de??µa (out order execution) e??aµe 1
Structural stall ?a? ?a???a ???? stall.
Ta µe?et?s??µe d?? e?d?? te??????
???aµ???? d??µ?????s? e?t???? (hardware)
Stat???? (shoftware/compiler)

• Scoreboard (e??tt?s? RAW stalls)
• Register Renaming
• a)Tomasulo
• ß)Reorder Buffer
• (e??tt?s? WAR ?a? WAW stalls)
• Branch prediction
• (e??tt?s? Control stalls)

• Loop Unrolling
• Software Pipelining
• Trace Scheduling

7
??a?t?se?? ?eta?? ??t???? (Depedences)

• ????? e??a? ?? p???? t?? stalls/bubbles ??t????
  p?? ???s?µ?p????? ?d???? registers.
• - ?a??????e? e?t???? µp????? ?a e?te?est???
  d?ad????? ????? ?a d?µ???????? stalls. ?.?.

DIV.D F0, F2, F4 ADD.D F10, F1, F3
- ??a?t?se?? µeta?? e?t???? µp????? ?a ?d???s???
se stalls. ?.?.
DIV.D F0, F2, F4 ADD.D F10, F0, F3
RAW

• ?? e?a?t?se?? µeta?? e?t???? pe????????? t??
  se??? e?t??ese?? t?? e?t???? (in order execution)
  p.?. ? ADDD p??pe? ?a e?te?este? µet? t?? DIVD
  st? 2? pa??de??µa. ??? pa??????e? e?t???? µp?????
  ?a e?te?est??? a??p?da (out of order execution)
  p.?. ? ADDD µp??e? ?a e?te?est?? p??? t?? DIVD
  st? 1? pa??de??µa.

8
??a?t?se?? ?eta?? ??t????

• Data Dependences ??? e?t???? e??a? data
  dependent ?ta? ?p???e? µ?a a??s?da ap? RAW
  hazards µeta?? t???.
• Name Dependences ??? e?t???? e??a? name
  dependent ?ta? ?p???e? ??a WAR ? WAW hazard
  µeta?? t???.
• L.D F0, 0(R1)
• ADD.D F4, F0, F2
• L.D F0, 0(R2)
• Control Dependences E?t???? e?a?t?µe?e? ap?
  branch e?t???.
• if p1 S1

9
?p????µe ?a ???s?µ?p???s??µe t? Hardware??a ?a
????µe CPI ???t? st? 1

• G?at? st? Hardware ?at? t?? e?t??es? t??
  p?????µµat??
• ????e?e? ?ta? de? ?????µe t?? p?a?µat????
  e?a?t?se?? ?at? t? compile.
• ? d???e?? t?? compiler e??a? p?? ap??.
• ? assembly ??d??a? µ?a? µ??a??? t???e? ?a?? ?a?
  se ????.
• ?d?a ??e?d? ?p?t?e?e e?t???? µet? t? stall ?a
  e?te????ta?
• DIV.D F0,F2,F4
• ADD.D F10,F0,F8
• SUB.D F12,F8,F14
• Out-of-order execution gt out-of-order completion.

10
???ß??µata µe Hazards.

• ??? eµp?d????µe WAR ?a? WAW hazards
• ?? ?????µe ??a t?? µetaß??t?? ?a??ste??se?? t??
  µ???d?? e?t??es??
• Forwarding t?? RAW hazards d?s????te??.

RAW
WAR
11
Scoreboard out of order execution

• ????sµ?? t?? ID stage sta d??
• ??d?s?/Issue?p???d???p???s? e?t????, ??e???? ??a
  structural hazards. In order instruction issue.
• 2. ??????s?/read operands??aµ??? µ???? ?a µ??
  ?p???e? data hazards, µet? d??ßase source
  registers. Out of order execution.
• ?? p??te? µ??a??? Scoreboards eµfa??st??a? µe t?
  CDC6600 t? 1963
• ??t???? e?te????ta? ?p?te de? e??a? e?a?t?µe?e?
  ap? p??????µe?e? e?t???? (p?? de? ?????
  e?te?este?) ?a? de? ?p?????? hazards.
• CDC 6600 In order issue, out-of-order execution,
  out-of-order commit (or completion)
• ?e? ?p???e? forwarding!

12
????te?t????? Scoreboard(CDC 6600)
Functional Units
Registers
SCOREBOARD
Memory
13
Scoreboard Implications

• Out-of-order completion gt WAR, WAW hazards?
• ??se?? ??a WAR
• Stall writeback st?d?? µ???? ?? registers ?a
  ????? d?aßaste?
• ??aßase registers µ??? ?at? t? Read Operands
  st?d??
• ??se?? ??a WAW
• ?????e?se hazard ?a? stall issue st?d??
  ?a??????a? e?t???? µ???? ? ???? e?t??? ?a
  e?te?este?.
• ?e? ?p???e? register renaming!
• ?????? e?t???? st? execution st?d?? gt multiple
  execution units or pipelined execution units
• ?? Scoreboard ??at?e? p????f???e? ??a t??
  e?a?t?se?? µeta?? t?? e?t???? p?? ????? ???e?
  issued.
• Scoreboard a?t??a??st? ID, EX, WB st?d?a µe 4
  st?d?a.

14
Four Stages of Scoreboard Control

• Issuedecode e?t??? ??e??e ??a structural
  hazards (ID1)
• Instructions issued in program order (for hazard
  checking)
• Dont issue if structural hazard
• Dont issue if instruction is output dependent on
  any previously issued but uncompleted instruction
  (no WAW hazards)
• Read operandspe??µe?e µ???? ?a µ?? ?p?????? data
  hazards, µet? d??ßase µetaß??t?? (ID2)
• All real dependencies (RAW hazards) resolved in
  this stage, since we wait for instructions to
  write back data.
• No forwarding of data in this model!

15
Four Stages of Scoreboard Control

• Execution e?t??es? st?? a???µ?t??? µ???da (EX)
• The functional unit begins execution upon
  receiving operands. When the result is ready, it
  notifies the scoreboard that it has completed
  execution.
• Write result????? ??t??es?? (WB)
• Stall µ???? ?a µ?? ?p???e? WAR hazards µe
  p??????µe?e? e?t?????a??de??µa DIV.D F0,F2,F4
  ADD.D F10,F0,F8 SUB.D F8,F8,F14CDC 6600
  scoreboard would stall SUBD until ADDD reads
  operands

16
3 µ??? t?? Scoreboard

• Instruction statusSe p??? ap? ta 4 st?d?a e??a?
  ? e?t???
• Functional unit status?e???e? t?? ?at?stas? t??
  functional unit (FU). 9 ped?a ??a ???e functional
  unit
• Busy Indicates whether the unit is busy or
  not Op Operation to perform in the unit (e.g.,
  or ) Fi Destination register Fj,Fk Source-r
  egister numbers Qj,Qk Functional units
  producing source registers Fj, Fk Rj,Rk Flags
  indicating when Fj, Fk are ready
• Register result status?e???e? p??? functional
  unit ?a ????e? ???e register, a? ?p???e? ??p??a.
  Blank when no pending instructions will write
  that register

17
?a??de??µa Scoreboard
18
Detailed Scoreboard Pipeline Control
19
?at?de??µa Scoreboard ?????? 1
20
?a??de??µa Scoreboard ?????? 2

• Issue ?e?te?? LD Structural Hazard.

21
?a??de??µa Scoreboard ?????? 3

• Issue MULT In order issue.

22
?a??de??µa Scoreboard ?????? 4
23
?a??de??µa Scoreboard ?????? 5
24
?a??de??µa Scoreboard ?????? 6
25
?a??de??µa Scoreboard ?????? 7

• ???ßasµa t?? t?µ?? t?? multiply? RAW Hazard.

26
?a??de??µa Scoreboard ?????? 8a
27
?a??de??µa Scoreboard ?????? 8ß
28
?a??de??µa Scoreboard ?????? 9
?????? ??t??es??

• ???ßasµa t?? t?µ?? t?? MULT SUB? Issue ADDD?

29
?a??de??µa Scoreboard ?????? 10
30
?a??de??µa Scoreboard ?????? 11
31
?a??de??µa Scoreboard ?????? 12

• ???ßasµa t?? t?µ?? t?? DIVD? RAW Hazard.

32
?a??de??µa Scoreboard ?????? 13
33
?a??de??µa Scoreboard ?????? 14
34
?a??de??µa Scoreboard ?????? 15
35
?a??de??µa Scoreboard ?????? 16
36
?a??de??µa Scoreboard ?????? 17

• G?at? ?a µ?? ??aft??? ta ap?te??sµata t?? ADD???

37
?a??de??µa Scoreboard ?????? 18
38
?a??de??µa Scoreboard ?????? 19
39
?a??de??µa Scoreboard ?????? 20
40
?a??de??µa Scoreboard ?????? 21

• WAR Hazard t??a e?afa??st??e...

41
?a??de??µa Scoreboard ?????? 22
42
?et? ap? µe?????? ???????
43
?a??de??µa Scoreboard ?????? 61
44
?a??de??µa Scoreboard ?????? 62
45
?a??de??µa Scoreboard ?????? 62

• In-order issue out-of-order execute commit

46
CDC 6600 Scoreboard

• Speedup 1.7 from compiler 2.5 by hand BUT slow
  memory (no cache) limits benefit
• Limitations of 6600 scoreboard
• No forwarding hardware
• Limited to instructions in basic block (small
  window)
• Small number of functional units (structural
  hazards), especially integer/load store units
• Do not issue on structural hazards
• Wait for WAR hazards
• Prevent WAW hazards