Test Resource Partitioning and Test Data Compression for SystemonaChip

1
Test Resource Partitioning and Test Data
Compression for System-on-a-Chip

• Anshuman Chandra
• Department of Electrical Computer Engg., Duke
  University.

2
Thesis Outline

• Test resource partitioning (TRP) using Golomb
  codes VTS00, TCAD01, DATE01,TCAD02
• TRP using Frequency-Directed Run-length (FDR)
  codes VTS01, DT01, VTS02
• Low-power Scan testing using Golomb codes
  DAC01, TCAD02
• TRP and Reduced Pin-Count testing using test data
  compression DATE02
• Low Power scan testing using Alternating FDR code
  Submitted to DAC02

3
Work objectives

• Present a new test resource partitioning (TRP)
  schemes for SOCs
• Based on compression schemes using
  variable-to-variable-length Frequency-Directed
  Run-length (FDR) code
• Providing very high test data volume compression
• Save ATE memory and reduce testing time
• Design a low-cost on-chip decoder for
  decompression of encoded test patterns

4
Presentation outline

• TRP for SOC designs
• TRP philosophy
• Basic concept of variable-to-variable-length
  codes
• Test data compression and decompression
• Test architecture and decompression scheme for
  core-based designs
• Testing time analysis
• Conclusions

5
System-on-a-chip (SOC)

• SOCs are complex designs combining logic, memory
  and mixed-signal circuits in a single IC
• Main SOC testing challenges
• Core level test Embedded cores are tested as a
  part of the system
• Test access Due to absence of physical access to
  the core peripheries, electronic access mechanism
  required
• SOC level test SOC test is a single composite
  test including individual core, and UDL test and
  test scheduling
• Test data volume for core-based SOC designs is
  very high.
• New techniques are required to reduce testing
  time, test cost, and the memory requirements of
  the automatic test equipment (ATE)

6
TRP for SOCs

• Partitioning and optimization of test resources
• Enhance test effectiveness
• Reduce test cost
• Reduce testing time

7
Growing Chip complexity and ATE Limitations
DSP core
Legacy core
Embedded RAM
8
TRP based Testing
Memory
CPU
Legacy
Embedded
core
RAM
I/O
controller
DSP
core
9
TRP Philosophy
Test resource partitioning
Hardware
Time
Data
10
SOC testing using External Tester
A conceptual architecture for testing
system-on-a-chip
11
SOC testing using Ext. Tester on-chip decoder
A conceptual architecture for testing
system-on-a-chip by storing encoded test data TE
in ATE memory and decoding it using on-chip
decoder.
12
Test Architecture
Internal scan chain
Decoder
TE
TD
Core under test
Test architecture based on FDR coding and the use
of internal scan chain(s).
13
Frequency-Directed Run-length (FDR) Codes

• Variable-to-variable-length code
• Designed for compressing test data
• Based on the distribution of runs of 0s
• More efficient than Golomb codes
• Compress TD

14
Distribution of Runs

• Key observations Frequency of runs of 0s of
  length
• High for 0 ? l ? 20
• Low for l gt 20
• For the range 0 ? l ? 20, frequency of runs of
  length l decreases rapidly
• Key lesson
• Better compression can be achieved if a short
  codeword is assigned to smaller runs of 0s

15
FDR Code Encoding Procedure
16
FDR Encoding Example
Encoded sequence corresponding to
0100000010001000000001is 101100001001110010
(22 bits)
(18 bits)
17
Code Comparison
18
Experimental Results Test Data Compression
250000
T
D
T
(Golomb
T
)
100
E
D
200000
T

(FDR
T
)
E
D
100
100
150000
72
No of bits
43
57
100000
100
39
50000
21
19
100
38
100
34
81
63
52
0
s5378
s13207
s15850
s35932
s38417
s38584
19
Results on Industrial Test Sets

• Two large designs from IBM
• Microprocessor design with 3.6 million gates and
  726000 latches
• On average, 97 compression was achieved
• ASIC design with 1.2 million gates and 32200
  latches
• On average, 95 compression was achieved

20
Probabilistic Analysis

• For a binary memoryless source with p as the
  probability of 0s, entropy H(p) is

H(p) plog2 p (1 p) log2 (1 p)

• Average codeword size for FDR code is given by

• Compression gain

21
Graphical Comparison-I
22
Graphical Comparison-II
23
Testing Time Analysis Single Scan Chain (TATSSC)
TATSSC
tshift
tdecode
tprefix
ttail
TATSSC tshift tprefix ttail
24
Upper bound on TATSSC- I
- Let t(k,i) be the time required to decompress
ith member of kth group
- Upper bound on TATSSC can be obtained by
assuming that decoding begins after complete code
word is transferred from the ATE
t(k,i) ? tshift(k,i) tdecode(k,i)
Time required to transfer the codeword
tshift(k,i) 2k / fATE
25
Upper bound on TATSSC- II
26
Upper bound on TATSSC- III
Let q(k,i) be the absolute frequency of the ith
member of kth group. Therefore, decompression
time for the runs belonging to kth group
Test application time is obtained by summing over
all the groups, i.e.,
27
Lower bound on TATSSC-I
Lower bound on TATSSC is obtained by assuming
that tail part is transferred while prefix is
being decoded. Therefore, decompression time for
the runs belonging to kth group
Test application time is obtained by summing over
all the groups i.e.,
28
Experimental Results Test Application Time
Comparison of testing time using proposed TRP
method to traditional scan based testing for ?
8 and fATE20 MHz
29
On-chip FDR Decoder

• Whenever the decoder receives group prefix, it
  outputs 0s equal to the binary number.
• The decoder starts tail decoding as soon
• as it receives a 0.
• The k-bit counter is used to count 0s being
• output by the FSM.
• The log2 k-bit counter is used to count the
• prefix length.
• The synthesized circuit for FSM contains 4
  flip-flops and 38 gates only.
• The decoder is independent of the CUT and the
  precomputed test set.

30
FDR decoder for TRP
fATE clock domain
kmax bit
log2 kmax bit
counter
counter
bit_in
FSM
en
fscan clock signal
fscan clock domain
out
Scan chain
31
Entropy Bound

• Theoretical lower bounds predicted by the entropy
  of test data
• Let TD contain run-lengths l1, l2, , lk and let
  p1, p2, , pk be the relative frequencies
  respectively
• Entropy of TD is given by

32
Entropy bounds and FDR code compression
90
Entropy bound
80
70
FDR codes
60
50
Percentage compression
40
30
20
10
0
s5378
s9234
s13207
s15850
s38417
s38584
33
Conclusions

• Test data compression can be used for effective
  test resource partitioning
• FDR codes can be used for efficient compression
  of test data
• Superior to Golomb and run-length codes
• Decompression logic small and easy to implement
• Scalable and independent of the CUT and
  precomputed test set
• Additional benefits decreased testing time, use
  of low-cost DfT testers, low-power scan testing

34
Thankyou