High Performance, High Reliability, MultiCore Design Methodology

1
High Performance, High Reliability, Multi-Core
Design Methodology

• Hyunchul Shin
• shin_at_hanyang.ac.kr
• Multi-Core Design Methodology
• Research Center
• Hanyang University

2
MPSoC Research is Important

• Multi-core Market Prospect (ref DIGITIMES)
• 2005 2.6 billion (14800 K ea)
• 2015 64.8 billion (638000 K ea)

3
MPSoC Technologies (1/3)

• picoArray
• (picoChip, England)
• In 2006, picoChip announced picoArray multi-core
  processor arrays, PC202, PC203, PC205, for next
  generation wireless.

• Nexperia
• (Philips, Holland)
• 32bit/64bit MIPS processors and 32bit/64bit
  Trimedia VLIW processors for MPEG-4, MPEG-2,
  Dolby Digital decoding,  MP3 decoding, and other
  multimeadia applications

4
MPSoC Technologies (2/3)

• OMAP (TI, U.S.A.)
• TI developed ARM Cortex-A8 core based OMAP
  processors, in March 2008

• Cell (IBM/Sony/Toshiba,
• U.S.A./Japan)
• A 64-bit Power architecture based processor and 8
  Synergistic Processor Units (SPUs) for
  heterogeneous chip multi-processors
• Clock speed over 4GHz. Performance 256 GFlops

5
MPSoC Technologies (3/3)

• 80-core (Intel, U.S.A.)
• Intel (2007) 4GHz 80-core processor consists of
  80 floating point cores.
• Cores with 5-port routers and PEs are connected
  by a mesh network. (.28 Teraflops)

• Cortex-A9 MPCore (ARM, England)
• ARM (2007) Cortex-A9 MPCore which is based on
  ARM MPSoC technology.

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Research Goals

• Multi-core architectures for various multimedia
  processing
• Mapping techniques of application algorithms to
  architectures
• Target compiler, RTOS
• Simulation, debugging
• Variuos yield-aware techniques for multi-core
  platform
• Soft error modeling, design to reduce soft errors

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Group 1 Multi-Core Architecture Mapping

• Studies on multi-core architectures
• Heterogeneous processor models
• Application algorithm to architecture mapping
• Interconnect bus/network design
• Memory module optimization
• Performance evaluation and enhancement
• Design for debug

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Mapping Algorithm to Architecture

• Static
• Dynamic

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Design for Debugging

• Typical design error
• Medical device to treat cancer, Therac-25,
  overexposed patients to radiation,
  injuring/killing 6 people between 1985 and 1987.
• FDIV bug in the Intel Pentium processors 475
  million to replace the products
• Starting a cars ABS unexpectedly
• How to fix the design errors found in front-end,
  logic, physical and post-silicon designs.
• Functional, electrical, and yield errors in
  designs.
• Automatic repair
• Manual repair
• Repair of functional and electrical errors
• Environment and tools
• Combination of simulation and formal verification
• Interactive verification and debugging
• Resynthesis
• Bug trace minimization

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Group 2 Multi-Core SW Development

• OS based on multi-core architectures
• Target compiler
• Debugger
• Simulator
• Simulator for reconfigurable processors
• Thermal simulator
• Power management for multi-core
• Optimal memory assignment
• CAD tools and design environment

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OpenMP Programming Model for Multi-Core
Split-up this loop between multiple threads
void main() double Res1000 pragma omp
parallel for for(int i0ilt1000i)
do_huge_comp(Resi)
void main() double Res1000 for(int
i0ilt1000i) do_huge_comp(Resi)

Sequential program
Parallel program
Fork-Join Parallelism
Master Thread
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DPM DVFS for Multi-Core
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Group 3 Yield Reliability Aware Design

• Yield-aware techniques
• High-level statistical system design methods for
  multi-core platform
• Libraries
• System level adaptive circuit technique methods
• Platform and general library for yield-aware
  support
• Design by using the yield-aware techniques
• System integration and performance evaluation

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Variability Crisis

• Aggressive technology scaling
• ? Rapidly increase of process variation
• Process variation induces chip performance
  variation ? Yield degradation
• Yield-aware design considering process variation
  Must in DSM era

Frequency and Leakage of Microprocessors in a
Wafer 0.18um, Intel
S. Borkar et al., Parameter variations and
impact on circuit and microarchitecture, DAC,
2003
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Yield Enhancement Techniques

• Statistical design
• Design-time yield enhancement techniques
• Analytically evaluate the probability for the
  design to meet the performance goals
• Parametric yield maximization variability
  minimization
• Adaptive circuit techniques
• Post-silicon yield enhancement techniques
• Real-time chip performance compensation through
  real-time monitoring of chip performance
• Platform integration
• High productivity and yield enhancement
• Systematic system-level yield management