Programmable Logic Devices

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Programmable Logic Devices

• ECET 1200

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Design Problem
Design an automobile hatch release that canbe
activated with
1. Interior Switch
2. RF Remote Control
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Design Problem
Steps in design process
1. Draw a system level design
2. Clearly define interface signals
3. Design the circuit
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Design Problem
System Level Design
Receiver
Transmitter
RF
RF
Active
HatchRelease
InteriorSwitch
Open
Active
GearPosition
Park
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Define Interface Signals
All interfaces should be clearly defined
beforework begins on the circuit design
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Design Problem
Determine Input/Output Relationships
E
R I
0
1
00
O ?...
01
11
10
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Design Problem
Standard Gate Implementation
I
E
O
R
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Programmable Logic Devices
Definition
A Programmable Logic Device (PLD) is a generic
term for a device containing anunstructured
array of logic gates. Most PLDs also include
more complex devices such asflip-flops.
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PLD Structure
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PLD Structure
Inverted and noninvertedversions of each input
areprovided
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PLD Structure
Each input is connected to a setof vertical
conducting paths
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PLD Structure
Each AND gate represents aproduct term in an SOP
expression
Shorthand Notation for a multiple inputAND gate
(e.g. 6 possible inputs in this example)
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PLD Structure
Output represents a completeSOP expression
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PLD Programming
The PLD is programmed byconnecting the
appropriate inputsto each product term AND gate
A
AB
B
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PLD Example
Program
R
I
O
E
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PLD Advantages
1. Reprogrammable - design changes easily
implemented - errors easily corrected
2. Reduce number of ICs used in design
3. Reduced stock requirements
4. Less PCB Area necessary for design
5. Less opportunity for assembly errors
6. Generally faster than TTL
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PLD Note
PAL, PLA, FPLA, and GAL are all PLDs butare
proprietary and represent specific
manufacturesproducts. They differ in features
and basicfunctionality.
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The GAL 22V10
1. General Structure
2. Logic Array
3. Macrocell Structure - Simple Mode - Complex
Mode - Registered Mode
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Programming PLDs with ABEL
Development Steps
1. Completely define inputs/outputs
2. Write equations to describe - logic
outputs - output enables (.OE) -
flip-flop inputs (.D)
3. Create source file (.pld)
4. Compile/Debug source file
5. Program PLD with JEDEC file (Joint
Electronic Device Engineering Council)
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ABEL Source File

• Header - basic info describing design
  - information only not used in compile

• Input pin definitions

• Output pin definitions

• Defining equations

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Equation Syntax

• Logic AND (e.g. AB)
  OR (e.g. AB)
  NOT ! (e.g. !A)
  XOR (e.g. AB)

• Enable ltpin_namegt.OE

• Latch ltpin_namegt.D

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Examples

• Basic Logic Example

• Truth Table Example

• State Machine Example

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Programmable Logic Devices

• ECET 1200