Application of FinFET Technology to AnalogRF Circuits Matthew Muh, Professor Ali M' Niknejad

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Application of FinFET Technology to Analog/RF
Circuits Matthew Muh, Professor Ali M. Niknejad
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Research plans

• Evaluating the suitability of FinFET technology
  for analog/RF circuits involves the following
• Developing a working model for SPICE simulation
  based on measurements and/or 3-D device
  simulation
• Finding optimal device layouts for high-frequency
  performance
• Designing, fabricating test circuits (e.g.,
  frequency divider, LNA, oscillator) and verifying
  speed, power gain, noise, linearity
• Refining device models based on circuit-level
  measurements
• Comparing utility of FinFET for different
  applications

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RF CMOS performance trends

• Effect of technology scaling on RF performance
• fT improves with scaling (proportional to 1/L
  in velocity saturation) assuming fT 75 GHz for
  a 0.13µm MOSFET, then fT 150 GHz for a 60-nm
  FinFET
• fMAX improves with scaling, but exhibits strong
  dependence on layout, gate resistance, and
  parasitics
• FMIN decreases with scaling for a given
  frequency due to increase in fT
• A sub-100nm advanced transistor structure
  (FinFET) should be able to take advantage of
  these RF scaling trends. Can it confer additional
  benefits to analog/RF circuits, such as improved
  gmro or linearity?

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High-frequency modeling

• Impact of gate resistance on RF performance
• if ignored, potential error in impedance matching
  (e.g., to a 50-O source)
• increased minimum noise figure
• reduced power gain, degraded overall
  transconductance
• fMAX
• Gate resistance modeling
• Rgate consists of two components
• distributed gate electrode resistance
• channel-induced gate resistance
• Minimize gate resistance by using
• proper layout (multi-finger design)
• silicided polysilicon gate/metal gate
  technologies
• Problem is alleviated in FinFETs utilizing metal
  gate to adjust Vt

Source Jin, IEDM98
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FinFET structure and layout

• The double-gate FinFETa promising candidate to
  continue CMOS scaling deep into the nanometer
  regime
• Gate straddles thin silicon fin, forming two
  conducting channels on sidewalls

3D view of FinFET

• Layout similar to bulk-Si MOSFET

Bulk-Si MOSFET
Multi-fin layout
Source (all images) T-J King, et al, FinFET
Technology Optimization presentation slides,
Oct. 2003
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Simulated n-FinFET high-frequency behavior

• Initial simulation results using BSIMSOI3.1
  model, adapted from preliminary SPAWAR FinFET
  model (extrapolated DC, estimated AC parameters),
  ignoring gate resistance
• Device exhibits high source/drain parasitic
  resistance
• Need an improved high-frequency device model

• W/L 1um/0.06um
• Ids 280uA
• Vgs Vds 1V

fT 34 GHz fMAX 82 GHz fT much lower than
expected
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FinFET modeling approach

• Need a suitable SPICE model for initial design
  based on transistor I-V and high-frequency AC
  characteristics

• Modeling approaches
• Small-signal equivalent model
• Uses simple lumped circuit elements
• Suitable for only selected bias points
• Avoids need for complete device model
• Valid only for small-signal operation
• Subcircuit model (adapt 60-GHz CMOS approach)
• Begin with core BSIMSOI model
• Extend core subcircuit with extrinsic parasitics
  (BSIMSOI3.1 already includes gate resistance
  model)
• DC I-V curve fitting to extract core BSIM
  parameters
• Small-signal Y-parameter fitting to extract
  parasitic component values
• Also suitable for large-signal simulation

Generic subcircuit model (core MOSFET shown in
color) (Adapted from S. Enami, C. Doan, V-Band
CMOS Mixers)
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Small-signal lumped-element model

• Performed 3-D device simulation to generate I-V
  and y-parameter curves
• Performed initial high-frequency curve fitting to
  obtain circuit parameters for basic small-signal
  model. Need to refine 3D device structure to
  obtain better accuracy.

W/L 0.1µm/0.065µm Vgs 1.5 V, Vds 1 V
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Test structures

• SCL static frequency dividera good benchmark for
  high-speed technologies
• UCB Microlab FinFET process, target gate length
  35 nm, fin thickness 20 nm, metal gate
  technology (polySi Mo)
• Circuit-level simulation using simple AHDL
  behavioral model based on device simulation
  results with lumped capacitances
• One-metal and two-metal versions, some rotated by
  45º to enhance NMOS mobility
• Individual transistors included for DC and
  S-parameter characterization

frequency divider schematic
Estimated maximum operating frequency near 40 GHz
for single metal version. Core divider power
consumption 6.6 mW
single metal layout (probe pads also utilize
second metal)
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Future work

• Investigate additional circuits, e.g., VCO, LNA
• Characterize individual transistors by measuring
  DC/AC behavior of fabricated devices
• Refine 3-D device simulations to improve
  accuracy, especially with respect to parasitic
  resistances and output resistance
• Build large-signal subcircuit BSIM model based on
  simulation results and/or measured data
• With an improved model, design additional
  analog/RF circuits for system-level verification
  of power gain, noise, etc.