USB 2.0 Technical Overview

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(No Transcript)
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USB 2.0 Technical Overview

• Brad Hosler
• USB Engineering Manager
• Intel Corporation

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Conference Goal

• Provide you with the information youneed to
  build USB 2.0 products
• USB 2.0 technical details
• USB 2.0 Infrastructure
• Building USB 2.0 devices
• USB 2.0 Building Blocks

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USB 2.0 Conference Agenda
Single Track Topics for Everyone

• Architecture Overview
• Peripheral Development Enabling
• Hi-speed power
• Hi-speed performance
• Microsoft SW Update
• USB 2.0 Compliance and Logo Program
• USB 2.0 Compliance Testing

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USB 2.0 Technical Agenda
Split Track Focused Topics

• USB2 Software
• Writing Quality Drivers
• HS Isoch Interface
• Building USB2 Devices
• Design Options
• Transceiver Macrocell
• Analyzers
• Platform Design
• BIOS considerations

• USB2 Specifications
• Electricals
• Protocol
• Hubs
• Power Management
• Host Controller Spec
• Compliance testing
• Cable Testing
• USB On the Go

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ArchitectureOverview
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USB 2.0 What Changed??
Architecture Overview

• Low level electricals for High Speed (HS)
  signaling
• Much higher bit rate (480Mb/s) requires new
  transmitter/receiver
• Hub changes for backward compatibility
• Features limit bandwidth impact of Full Speed
  (FS)and Low Speed (LS) devices on HS devices
• FS/LS devices consume a bit-rate equivalentof HS
  bandwidth

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USB 2.0 What Didnt Change?
Architecture Overview

• Same host/device model
• Host is in charge
• Devices are inexpensive
• Same basic protocol
• Token, data, handshake
• Same device framework
• Descriptors
• Same software interfaces
• USBDI

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USB 2.0 What Didnt Change?
Architecture Overview
Continued

• Same power distribution and consumption
• 500ua suspend, 100ma unconfigured,500ma
  configured
• Same power management features
• Suspend/resume model unchanged
• Same topology management
• Hub features to handle connect,
  disconnect,enable, disable,
• Same cables and connectors

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Sample USB 2.0 Topology
Architecture Overview

• Hub provides high-speed expansion (ala USB 1.1
  hub)
• Hub provides additional Full/Low speed bus(es)

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USB 2.0 Host Controller
Architecture Overview

• Allows port functionality regardless of OS
  version
• USB 1.1 OS will just work as USB 1.1 ports
• USB 1.1 HCs can go away over time
• Replaced with integrated USB 2.0 Hub

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USB 2.0 Hub
Architecture Overview

• Hub controller same as USB1.1
• Routing logic connects device to appropriate path

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Transaction Translator (TT)
Architecture Overview

• TT handles low/full speed transactions
• Driven with split transactions
• Start-Split
• Host tells Hub to initiate full/low speed
  transaction
• Complete-Split
• Host asks Hub for results of previous
  full/lowspeed transaction

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Bandwidth Usage
Architecture Overview

• Low/full speed devices use bit-rate equivalent of
  USB2.0 bandwidth
• 6Mbps classic camera (50 of classic) uses less
  than 2 of USB2.0 bandwidth (6Mbps/480Mbps)

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ISOCH IN through a TT
Architecture Overview
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Summary
Architecture Overview

• Two major changes for USB 2.0
• Higher speed electricals
• Transaction translator in USB2.0 hub
• Backward compatibility
• All Full/Low-speed devices continue to work
• Has little impact on HS bandwidth

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Enabling Peripheral Development
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USB 2.0 HC Cards
Peripheral Enabling

• PCI and PCCard versions
• Use NEC silicon
• Full EHCI implementation
• Available in retail
• Frys, Circuit City,
• www.orangemicro.com,www.adaptec.com,

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Driver Software
Peripheral Enabling

• HC driver for Windows 2000 and Windows XP
• Available at www.usb.org for member companies
• Drivers provide full functionality
• All high-speed transfer types
• Full support for USB 2.0 hub transaction
  translator
• Drivers are for development use only
• Cannot be shipped with products

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Single Transaction Tool
Peripheral Enabling

• Software application for generating individual
  high-speed transactions
• Very useful for early device debug
• Doesnt require a device to enumerate
• Any type of transaction can be generated
• Including individual parts of Control transfers
• Available at www.usb.org

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Transceiver Macrocell
Peripheral Enabling
Defines Standard Interfacefor Transceiver
Macrocell

• USB 2.0 Transceiver Macrocell Interface (UTMI)
  http//developer.intel.com/technology/usb/spec.htm
  
• Broad Industry support
• Discrete versions available

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VHDL (IP) Cores
Peripheral Enabling
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Building Blocks
Peripheral Enabling

• Microcontrollers
• Cypress
• Interface chips
• Netchip
• IDE/ATAPI bridges
• In-System Design, NEC
• ENET 10/100 Bridge
• Kawasaki LSI

• UTMI macro cells
• Seiko-Epson, Kawasaki LSI
• UTMI Transceivers
• Lucent, Kawasaki LSI

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Bus Analyzers
Peripheral Enabling

• Available now
• Catalyst
• http//www.catalyst-ent.com
• CATC
• http//www.catc.com
• Crescent Heart
• http//www.c-h-s.com
• Data Transit
• http//www.data-transit.com

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Peripheral Integration Lab
Peripheral Enabling

• Integration lab at Intels Architecture Labsin
  Oregon
• Multiple hosts and devices (interop testing)
• Test equipment (scopes, analyzers, TDRs, etc.)
• Expert help from HW and SW engineers
• Compliance testing
• Platforms and host controllers welcome too
• Available to anyone planning on deliveringUSB
  2.0 device in 2001

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Hi-Speed Power Issues
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Power Requirements
Hi-Speed Power

• Suspended - 2.5ma
• Configured - 500ma
• UnConfigured - 100ma
• Examine each of these from a hi-speed device and
  infrastructure (host, hub, cable) perspective

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Suspend Current
Hi-Speed Power

• Device
• Device is always in FS mode, HS clocks are off
• Implementations should be similar to current
  solutions
• Host/Hub
• Important for Instantly Available PCs
• Dual-mode power supplies are sized to provide
  power to USB port when machine is sleeping
• Dont care for hubs and cables

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Configured Current
Hi-Speed Power

• Device
• Hi-speed transceivers tend to consume more power
• Less power available for device function
• Host/Hub
• Power supplies sized to support this
• Cable conductors sized for appropriate IR drop

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Unconfigured Current
Hi-Speed Power

• Device
• Hi-speed transceiver can consume most of budget
• Difficult to build bus-powered hi-speed devices
• Host/Hub
• Important for bus-powered hubs
• Four downstream ports at 100ma each
• Dont care for hosts, self-powered hubs, and
  cables

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Issues
Hi-Speed Power

• We like bus-powered devices
• This is an essential characteristic for products
• Is the 100ma limit really a problem?
• Transmit/receive differences
• Device is gt99 receiving when unconfigured
• Would increasing to 150ma be enough?
• Impacts bus-powered hubs
• Limited to two ports (300ma for ports, 200 for
  hub silicon)
• Any other impacts?

Comments/suggestions to electricals_at_usb.org
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Hi-Speed Detection Handshake
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Downstream Ports
Hi-Speed Handshake

• Port is driving RESET
• Port must detect 2.5us ChirpK starting from 2.5us
  after asserting RESET until 7ms after asserting
  RESET

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Upstream Ports
Hi-Speed Handshake

• Two cases Reset from FS and reset from HS
• Both cases
• ChirpK must be at least 1ms in duration and must
  be complete within 7ms after RESET began
• Reset from FS
• Device must start ChirpK sometime between 2.5us
  and 6ms after detecting RESET
• Reset from HS
• After device sees SE0 for 3ms and reverts to FS
  terminations, then does ChirpK if there is still
  an SE0

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Reset from HS
Hi-Speed Handshake
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Hi-Speed USB Performance
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Mass Storage Performance
Hi-Speed USB Performance

• Standard IDE drive connected through different
  means

Connection Read (MB/s) Write (MB/s) Seek Time (msec)
USB 2.0 12.1 9.9 13.5
USB 1.1 0.92 0.88 15.4
IDE same bus 2.1 2.0 14.2
IDE separate bus 15.1 13.6 12.3
Values measured with HD Tach 2.61, 30GB IBM
drive, 333Mhz PIII system, 320MB RAM
Data provided by In System Design.
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Mass Storage Performance
Hi-Speed USB Performance

• Benchmark comparison of USB 2.0 high-speed USB
  drive with IDE drive

Benchmark PIO-3 PIO-4 UDMA USB1
Business Disk WinMark 99 105 106 90 260
High-End Disk WinMark 99 155 154 95 534
Data provided by Quantum Corp.
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CD/RW Performance
Hi-Speed USB Performance

• Time comparison for reading and writing an audio
  CD
• Time to copy data CD 6m 28s
• USB2 to USB2

USB1 IDE USB2
Rip an audio CD 15m 6m 40s 3m 15s
Write an audio CD 24m 6m 10s 4m 20s
P4 system, 128MB, 1.3GHz . TDK 16/10/40 CDRW.
In System IDE bridge.
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Summary

• Everything you need to develop USB2 productsis
  available
• Tools, host controllers, building blocks,
  analyzers
• Building bus-powered high-speed productsis
  difficult
• Is a change to unconfigured power limit needed?
• High-speed products deliver great performance
• Comparable to inside-the-box performance