The Processor: Datapath and Control

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??? ?? ??Lecture 9

• The Processor Datapath and Control
• Oct. 24, 2008
• ? ??

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In This Lecture

• Abstract view of the processor
• Building blocks
• Register file
• ALU, multiplexor, memory, adder, sign-extender
• Single-cycle datapath
• Control

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The Processor Datapath Control

• We're ready to look at an implementation of the
  MIPS
• Simplified to contain only
• memory-reference instructions lw, sw
• arithmetic-logical instructions add, sub, and,
  or, slt
• control flow instructions beq, j
• Generic Implementation
• use the program counter (PC) to supply
  instruction address
• get the instruction from memory
• read registers
• use the instruction to decide exactly what to do

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MIPS Datapath and Control
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Abstract View of the Implementation

• Two types of functional units
• elements that operate on data values
  (combinational logic)
• elements that contain state (state elements)

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State Elements

• Clocks used in state elements
• when should an element that contains state be
  updated?
• Level-sensitive latch
• Edge-triggered flip-flop

(cycle time)
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D flip-flop

• Output changes only on the clock edge

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Our Implementation

• An edge triggered methodology
• Typical execution
• read contents of some state elements,
• send values through some combinational logic
• write results to one or more state elements

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Register File read

• Built using D flip-flops
• A register 32 D flip-flops
• Register file 32 registers
• Two register addresses and two data outputs
  (because an R-type instruction requires two
  resister data for operands)

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Register File - write

• Thus, a register file requires
• Three addresses, two for read and one for write
• RA, RB, RW
• One data input for write
• busW
• Write enable
• Two data output
• busA, busB
• Clock

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Timing Diagram of Register File
RW
RA
RB
Write Enable
5
5
5

• read is simply combinational
• write is edge-triggered

busA
busW
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32 32-bit Registers
32
busB
Clk
32
Clk
access time
RA
7
12
27
data of Reg7
BusA
data of Reg12
RW
15
22
18
BusW
456
-6822
123
933
474
Write Enable
Data is written here Reg18 933
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Elements for Instruction Fetch

• Basic Instruction Fetch Unit

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Elements for R-format Instructions

• Two elements for R-format
• Rrd lt- Rrs op Rrt

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Elements for Load/Store Instuctions

• Additional elements for Load/Store
• Rrt lt- MemRrs SignExtimm16

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Datapath for a Branch (beq)

• If (Rrs Rrt)
• PC lt- PC 4 ( SignExt(imm16) x 4 )
• Else PC lt- PC 4

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Datapath for lw/sw and R-type
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Putting it Altogether
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Control

• Selecting the operations to perform (ALU,
  read/write, etc.)
• Controlling the flow of data (multiplexor inputs)
• Information comes from the 32 bits of the
  instruction

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Three Instruction Classes

• Op. 6 bits and funct. 6 bits can be used to
  generate control signals
• I-type an J-type instructions only have op. 6
  bits
• R-type instructions have both op. 6 bits and
  funct. 6 bits

R I J
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Control with Local Decoding
Main Control
ALU Control
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ALU Control (ALUctr)
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Truth Table for ALU Control

• Can turn into gates

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Control for R-type Instruction
op
rs
rt
rd
shamt
funct
Field
3126
2521
2016
1511
105
50
bit position

• ALUSrc 0
• ALUOp 10
• MemtoReg 0
• RegDst 1
• RegWrite 1
• MemRead 0
• MemWrite 0
• Branch 0

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Control for load instruction
op
rs
rt
address
Field
3126
2521
2016
150
bit position

• ALUSrc 1
• ALUOp 00
• MemtoReg 1
• RegDst 0
• RegWrite 1
• MemRead 1
• MemWrite 0
• Branch 0

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Control for branch equal
op
rs
rt
address
Field
3126
2521
2016
150
bit position

• ALUSrc 0
• ALUOp 01
• MemtoReg X
• RegDst X
• RegWrite 0
• MemRead 0
• MemWrite 0
• Branch 1

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Datapath Extended for jump

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Truth Table for Main Control
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Control Implementation

• Simple combinational logic (truth tables)

PLA Implementation
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Our Simple Control Structure

• All of the logic is combinational
• We wait for everything to settle down before we
  execute the next instruction
• Cycle time determined by length of the longest
  path (lw in this case)

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Performance of Single Cycle Datapath

• Calculate cycle time assuming negligible delays
  except
• memory (200ps), ALU and adders (100ps),
  register file access (50ps)
• Minimum Cycle Time gt 600ps!

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Where we are headed

• Single Cycle Problems
• what if we had a more complicated instruction
  like floating point?
• wasteful of cycle time
• One Solution
• use a smaller cycle time
• have different instructions take different
  numbers of cycles
• a multicycle datapath

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HW 4

• Exercise 4-10, 14, 17, 45, 46
• Due on 11/4 (Tue)