The Control Unit of Tiny Mips Processor

1
The Control Unit of TinyMips Processor
2
DATAPATH Tiny Mipsreview and completion as prep
for the control
3
Fetch part of the datapath for Tiny Mips
PC

D
D
Q
alu
1
opcode
address
Instruction memory
opcode
alu
4
Fetch part of the datapath for Tiny Mips Fetch
part accommodates also branching
5
PC

D
Q
alu
1
control
D
opcode
address
2-bit first operand info
Instruction memory
2-bit second operand info
Sel Reg For Read Port A
Sel Write Reg
opcode
Port A
alu
Sel Reg For Read Port B
WriteReg
we
Port B
Write data
alu
Register File Four 4-bit regs
Datapath for add, sub, or, and, not for Tiny
Mips
6
PC

D
Q
alu
1
control
D
opcode
address
2-bit first operand info
Instruction memory
2-bit second operand info
Sel Reg For Read Port A
Sel Write Reg
ALU operation
opcode
Port A
alu
Sel Reg For Read Port B
WriteReg
we
Port B
Write data
alu
Register File Four 4-bit regs
Datapath for add, sub, or, and, not for Tiny
Mips
7
Datapath for add, sub, or, and, not for Tiny
Mips in Digital Works Fetch Part accommodates
Branching
Digital Techniques Fall 2007 André Deutz, Leiden
University
8
PC

D
Q
alu
1
control
D
opcode
address
2-bit first operand info
Instruction memory
2-bit second operand info
Accommodates ldi
Accommodates ldui
ALUsource
Sel Reg For Read Port A
Sel Write Reg
ALU operation
opcode
Port A
alu
mux
Sel Reg For Read Port B
0
WriteReg
we
Write data
ALUsource
alu
Register File Four 4-bit regs
Port B
0
Datapath for add, sub, or, and, not, ldi, ldui,
mv for Tiny Mips
9
PC

D
Q
alu
1
control
D
opcode
address
2-bit first operand info
Instruction memory
2-bit second operand info
ALUsource
Sel Reg For Read Port A
Sel Write Reg
ALU operation
opcode
Port A
alu
mux
Sel Reg For Read Port B
0
WriteReg
we
Write data
ALUsource
alu
Register File Four 4-bit regs
Port B
0
Datapath for add, sub, or, and, not, ldi, ldui,
mv for Tiny Mips
10
Datapath for add, sub, or, and, not, ldi, ldui,
mv for Tiny Mips Digital Works (includes
also breq and unconditional jump, see Also next
slide for this)
Digital Techniques Fall 2007 André Deutz, Leiden
University
11
PC

D
Q
alu
1
control
opcode
address
first operand info
Br Uncond
Instruction memory
second operand info
setEqual
clock
BreqSwitch
ALU operation
ALUsource
Sel Reg For Read Port A
Sel Write Reg
Port A
alu
mux
Sel Reg For Read Port B
0
WriteReg
we
Write data
ALUsource
Register File Four 4-bit regs
Port B
0
Datapath for add, sub, or, and, not, ldi,
ldui,mv, breq, br for Tiny Mips
12
PC

D
Q
alu
1
opcode
address
first operand info
Br Uncond
Instruction memory
control
second operand info
setEqual
clock
BreqSwitch
Sel Reg For Read Port A
Sel Write Reg
Port A
alu
mux
Sel Reg For Read Port B
0
we
Write data
Register File Four 4-bit regs
Port B
0
Datapath for add, sub, or, and, not, ldi, ldui,
mv, breq, br for Tiny Mips
13
PC

D
Q
alu
1
control
D
opcode
address
2-bit first operand info
Instruction memory
2-bit second operand info
ALU operation
WriteMem
ALUsource
MemToReg
Sel Reg For Read Port A
Sel Write Reg
opcode
Port A
alu
mux
Read Data
Sel Reg For Read Port B
0
Address
WriteReg
we
Write data
ALUsource
alu
Data Memory
Register File Four 4-bit regs
Write Data
Port B
mux
0
ReadMem
Datapath for add, sub, or, and, not, ldi,
ldui,mv, ld, st for Tiny Mips
14
PC

D
Q
alu
1
control
D
opcode
address
2-bit first operand info
Instruction memory
2-bit second operand info
ALU operation
WriteMem
ALUsource
MemToReg
Sel Reg For Read Port A
Sel Write Reg
opcode
Port A
alu
mux
Read Data
Sel Reg For Read Port B
0
Address
WriteReg
we
Write data
ALUsource
alu
Data Memory
Register File Four 4-bit regs
Write Data
Port B
mux
0
ReadMem
Datapath for add, sub, or, and, not, ldi, ldui,
mv,ld, st for Tiny Mips
15
Data path Tiny Mips

• Merge the two previous data paths to get the full
  data path for TM

16
Control for Tiny Mipswhich is single cycle

• How do we construct the control unit?
• Wc can specify the control with Truth Tables
• Disadvantages of single cycle
• Control for multi-cycle processor the control is
  specified by
• FSM (finite state machine), or alternatively
• Microprogramming

17
Control Macro for TM
18
Tiny Mips Processor