A Computer Aided Engineering System for Memory BIST

1
A Computer Aided Engineering System for Memory
BIST

• C.C. Su, S.C. Hsiao, H.Z. Zhau, and C.L. Lee

Dept. of Electrical Engineering National Central
University Chung-Li, Taiwan 320
Dept. of Electrnoic Engineering National
Chiao-Tung University Hsin-Chu, Taiwan 300
2
Purposes

• Propose a Memory BIST Architecture
• Develop a Memory BIST CAE System
• Prototype it using MuP21 and FPGA

3
Contents

• Introduction
• Memory BIST Architecture
• Memory BIST CAE System
• Hardware Emulation Experiment
• Conclusions

4
Introduction

• For SoC, the integration of memory and logic
  poses a significant challenge for design,
  manufacturing, and test as well.
• Due to its smaller feature size than logic
  circuit, embedded memories are more likely to be
  affected by process imperfection.
• Embedded memory testing is critical for function
  verification.
• The memory test methodology is one of the major
  issues in SoC testing.

5
Introduction

• Most embedded memories cannot be accessed from
  the chip boundary.
• With limited I/O access, Built-in Self-Test
  (BIST) is an effective solution.
• An SoC has embedded memories of different sizes,
  organizations, and technologies.
• Diagnosis capability is crucial for yield
  improvement.
• Dedicated memory BIST is difficult to feature
  diagnosis capability.
• Therefore, flexible memory BIST with diagnosis
  capability is desirable.

6
Contents

• Introduction
• Memory BIST Architecture
• Memory BIST CAE System
• Hardware Emulation Experiment
• Conclusions

7
Introduction - Memory BIST CAE System
Memory BIST CAE System
TG Code Gen
MPU Code Gen
Interface Circuit Gen
Mem FS
TG Parser
Prog. TPG
Intf. CKT
Mem DUT
TG Editor
MPU
Memory BIST Architecture
8
Memory BIST Architecture
Prog. TPG
Intf. CKT
Mem DUT
MPU
Memory BIST Architecture
9
Memory BIST Architecture
Memory BIST CAE System
MPU Code Gen
TG Code Gen
Intf Ckt Gen
TG Parser
Mem FS
Prog. TPG
Intf. CKT
Mem DUT
TG Editor
MPU
Memory BIST Architecture

• A MPU core for test control and external
  interface.
• A Programmable TPG for test pattern generation.
• A Memory Interface Circuitry for customization.

10
Memory BIST - Hardware Architecture
MuP21 compiles test algorithm with its high level
Forth Language. FPGA roles as a coprocessor which
generates test pattern and timing for various
types of DUTs.
11
Memory BIST - MuP21 Processor
Address Bus
Data Bus
_at_,_at_,! ,!
1
1
Jump, T0,C0
A
P
Address Register
Program Counter
a!

a
call
5-Deep Data stack
4-Deep Return Stack
dup
pop
T
S
S1
R
R1
S2
R2
over drop
push
4 Classes of Instructions Total 25 Machine Code
Register Instruction Transfer Instruction ALU
Instruction Memory Access Instruction
_at_,_at_,n
ALU
Arithmetic Logic Unit
,n,com,2,2/,-or,and
! ,!
12
Memory BIST - MuP21 Processor

• Stack Architecture
• Minimal Instruction Set Computer
• 25 machine codes and 31 primitive words.
• 5-level data stack and 4-level return stack.

A
P
T
S
S1
R
R1
S2
R2
ALU
13
Memory BIST - MuP21 Processor
Address Bus
Data Bus
_at_,_at_,! ,!
1
1
Jump, T0,C0
A
P
Address Register
Program Counter
a!

a
call
5-Deep Data stack
4-Deep Return Stack
dup
pop
T
S
S1
R
R1
S2
R2
over drop
push
4 Classes of Instructions Total 25 Machine Code
Register Instruction Transfer Instruction ALU
Instruction Memory Access Instruction
_at_,_at_,n
ALU
Arithmetic Logic Unit
,n,com,2,2/,-or,and
! ,!
14
Memory BIST - TG and Interface Circuitry
OSC4
Command
Command
Decoder
RESET
Refresh
Counter
/WE
S
Column Bias
IO
IO
Address
D
Register
Address
Address
R
51_IO
Generator
Decoder
Row Bias
A

Register
A9,A1-0
M
Control
Unit
D9-0
Data
Data
DA19-10
Data Generator
Background
Register
Indicators
Data
Comparator
15
Contents

• Introduction
• Memory BIST Architecture
• Memory BIST CAE System
• Hardware Emulation Experiment
• Conclusions

16
Introduction - Memory BIST CAE System
Memory BIST CAE System
TG Code Gen
MPU Code Gen
Interface Circuit Gen
Mem FS
TG Parser
Prog. TPG
Intf. CKT
Mem CUT
TG Editor
MPU
Memory Test Architecture
17
Memory BIST CAE System

• Memory Module Technology Files
• Fault List Files
• Test Algorithm Files
• Test Algorithm Compiler
• Scanner
• Parser
• Code Generator
• Memory Fault Simulator

Memory BIST CAE System
MPU Code Gen
TG Code Gen
Intf Ckt Gen
TG Parser
Mem FS
TG Editor
18
Memory BIST CAE System
19
CAE System - Memory Technology File
20
CAE System - Fault List
? Single-Cell Faults
? Stuck-at fault (SAF) -- SA0, SA1 ? Transition
fault (TF) -- lt?/0gt, lt?/1gt ? Read disturb fault
-- ltr0/?gt, ltr1/?gt
? Multiple-Cell Faults
? Inversion coupling fault (CFin) -- lt?invgt,
lt?invgt ? Idempotent coupling fault (CFid)--
lt?0gt, lt?1gt, lt?0gt, lt?1gt ? Bridging fault (BF)
-- ABF, OBF ? State coupling fault
(SCF)--lt00/1gt,lt01/0gt,lt10/1gt,lt11/0gt ? Disturb
fault (CFds) -- ltr0?gt, ltr0?gt, ltr1?gt, ltr1?gt
ltw0?gt,
ltw0?gt, ltw1?gt, ltw1?gt
21
CAE System - Fault List Editor
22
CAE System - Fault Editor
23
CAE System - Test Algorithm File
Ex.
? Grammar
ltelement-listgt ltelementgt ltelement-listgt
ltelementgt ltelementgt U(
ltoperation-listgt ) D( ltoperation-listgt
) ltoperation-listgt ltoperationgt ltoperationgt,
ltoperation-listgt ltoperationgt wltdatagt
rltdatagt ltdatagt 0 1 2 3
9 ltpage sizegt Page ltdatagt
ltburst lengthgt Burst ltdatagt
? Tokens
Page Burst U D ( ) w r
, data \
24
CAE System - Test Compiler - Scanner
Page Burst U D ( ) w r , data
Token
Code
0 1 2 3 4 5 6 7 8 9 10
11
0 11 3
15 11 3
0 11 2
Token specifier
2 2
5 2
9 2
3 3
4 3
7 3
8 3
6 3
5 3
9 3
6 2
4 2
Token type
Line
25
CAE System - Test Compiler - Parser
Ex.
U ( r0, w1, r1 )
ltelementgt
26
CAE System - Test Compiler - SDRAM Model
27
CAE System - Test Compiler - SDRAM Model
28
CAE System - Test Compiler - Code Generation
?(w0101) ?(r0101, w1010) ?(r1010, w0101, r0101)
? Element chain
29
CAE System - Fault Simulator
30
Contents

• Introduction
• Memory BIST Architecture
• Memory BIST CAE System
• Hardware Emulation Experiment
• Conclusions

31
Hardware Emulation
32
Emulation - Hardware Architecture
33
Emulation- Signal Flowchart
34
Emulation- Hardware Organization
35
Emulation - MuP21 Board
36
Emulation - Memory BIST Board
37
Contents

• Introduction
• Memory BIST Architecture
• Memory BIST CAE System
• Hardware Emulation Experiment
• Conclusions

38
Conclusions

• Presented a flexible memory BIST architecture
• A simple processor for test flow control
• A programmable logic for test pattern and
  interface signal generation.
• It has a flexible architecture to target memories
  with different sizes and organizations.
• Diagnosis program can be down loaded on line.
• Implemented a CAE system in 9000 lines of C
  codes for automatic test code and netlist
  generation.
• The system has been verified through hardware
  emulation on commercial SDRAM.