Inspektor Test Jagt Defekte

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Inspektor Test Jagt Defekte

• Dr. Bernd Koenemann

Testviewz.com 2007
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About Me

• 1974 Diplom-Physiker, TU Braunschweig
• 1977 Dr. rer. nat., TU Braunschweig
• 1978-80 RWTH Aachen (ITHE, Prof. W. Engl)
• 1980-84 Honeywell, Minneapolis MN
• 1984-95 IBM, Poughkeepsie/East Fishkill NY
• 1995-99 LogicVision, San Jose CA
• 1999-02 IBM, San Jose CA
• 2002-04 Cadence Design Systems, San Jose CA
• 2004-05 Mentor Graphics, San Jose CA
• 2005- Dolce Far Niente, San Jose CA/Cartagena
  de Indias

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Web-Presence

• Professional
• http//www.testviewz.com
• Presentations, papers
• Personal
• http//www.koenemann.org
• Photos, videos, music

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Overall Context
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Why Do We Need Manufacturing Test?
Perfectby design
Defects !!!
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Defect Types and Potential Sources
Static
Environmental (Vdd, T, PLL, SEU)Coupling Noise,
Signal IntegrityHotE, Electromigration, Negative
Bias Threshold Instability (NBTI)
? Particle and otherSingle Event Upsets (SEU)
Dynamic
From R.Puri, IBM
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Static Variability

• Overall static variability is on the rise

From S. Nassif, ISPD 2004
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Dynamic Variability

• Voltage
• Activity change
• Power deliveryRLC
• Dynamicns to 10-100 uSec
• Within die
• Temperature
• Change in activity and ambient
• Dynamic 100s of uSec to mSec
• Within die

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Design Changes Due to Variability
System
Logic
Circuit
Deterministic
Layout
Models
Manu-facturing
Characterization
From R.Puri, IBM
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What Does That Mean?

• Yield limiters may buried inside the product
  design
• Very context-sensitive and design specific
• Non-visual and not represented in test vehicles

WorstCaseSpec
StatisticalSpec
EDAModel
Probability
Parameter
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Design versus Reality
Manufacturing
Design
Reality Check?
Reality Check?
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Defect Learning

• Background
• Inspection/metrology
• Test/characterization Vehicles
• Yield management systems
• Enhanced learning with test
• Debug/diagnostics/failure-analysis
• Statistical processing

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Inspection/Metrology

• Scanning for visible defects (mask/wafer)
• Special equipment
• Creates defect maps
• Measurement/tracking of process parameters
• Metrology equipment for specific process issues
  (e.g., surface planarity, oxide thickness, etc.)
• Equipment logs
• Measurement of circuit parameters
• Scribe-line (KERF) monitors
• Dedicated monitor structures
• On-chip monitors (e.g., PSRO, etc.)

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In-Line Inspection (Surface Scan)
Equipment
Results File
e.g., Defect x-y-coordinates Defect size Defect
classification Etc.
Detailed Image
Wafer Map Image
From Multiple Sources
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Test Vehicles

• Simple monitor structures for specific defect
  types
• E.g., metallization, vias, contacts, etc.
• Sophisticated design/process characterization
  monitors
• E.g., multiple defect types, representative of
  design/library elements, etc.

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Simple Serpentine Test Structure

• Suitable for measuring metallization defect
  densities

From Hess, et al., 2001
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Yield Management Systems

• Infrastructure for monitoring and analyzing yield
  issues
• Data collection
• Data warehousing
• Data mining/analysis
• Increasingly comprehensive
• Many data types (e.g., logistics, equipment,
  metrology, binning, etc.)
• Many analysis routines (e.g., queries, report
  generation, visualization, alert automation,
  etc.)
• Customizable (e.g., database extensions,
  scripting/APIs, etc.)

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Example Data Visualization (from Test)
Source, R. Madge, ITC 2004
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The New Role of Test

• Classical Yield Management Systems provide lots
  of wafer-level information, but lack intra-chip
  resolution
• Test observes chip-internal fail behavior that
  could help uncover the statistical impact of new
  catastrophic and parametric defect sources inside
  the chips
• By adding statistical analysis capabilities, test
  can become a key tool for statistical
  design/yield learning

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Test and Diagnostics
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Diagnostics

• Finding the root-cause of a particular test fail
• Characterizing the failing behavior
• Localizing the most likely problem area
• Integral part of
• Silicon debug
• Failure analysis

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Example
From A. Weber, Semi International, 2004
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Logic Diagnostics and Failure Analysis

• Log some number of fail sets from test
• Run logic fault isolation software
• Create gate-level callouts (net/pin names, fail
  type) most likely near the problem area
• Visualize callouts in layout
• Requires link between gate-level netlist and
  layout (e.g., from running LVS)
• Overlay callouts with defect maps or other
  information
• Requires translation to/from wafer-level
  coordinates
• Initiate Failure Analysis (FA)

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Fault Isolation Software
Netlist,Fault Models
Fault Simulation
Simulatedfail sets
TestPatterns
Compareandrank
Callouts
ATE/BIST
Fail sets
Note Fault simulation can be run ahead of time
to pre-calculate a fault dictionaryor after the
fact during diagnostics
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Callout Example
Note from IBM TestBench
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Logic Bitmapping
Fail Net Visualization
Note from LSI Logic
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Statistical Diagnostics for Logic

• Emerging defect/yield learning method for complex
  logic designs
• Implement comprehensive fail set logging for
  initial ramp and for volume production test
• Run logic fault isolation on all fail sets (could
  be thousands per day)
• Write all callout information into database
• Statistically sort, analyze, and visualize the
  cumulative callout information, e.g.,
• Query by cell-type, cell-instance/location, etc.
• Stack results on chip layout, reticle, and/or
  wafer map
• Compare with yield predictions
• Etc.

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Example Stacked Callout Visualization
Note from LSI Logic
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State of the Art

• Statistical diagnostics of logic fails are a
  rapidly emerging design/defect learning
  technology
• Learning design-specific issues from product
  chips
• Statistical relevance with large number of
  samples
• Complement/enhance existing fab-oriented yield
  management systems
• Add intra-chip resolution and visibility
• Complement/enhance DFM and yield modeling
• Provide feedback and calibration
• Most existing solutions are home-grown at IDMs
• Challenging data security/access issue for
  fabless/foundry
• No integrated commercial solution yet

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Vision of an Integrated Solution
Yield Management
Debug/FA Lab
Applications
Applications
APIs/Utilities
APIs/Utilities
Design Database
Data Warehouse
WIP, Metrology, Test,
Design, design analysis,
Inspection, etc.
design intent, etc.
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The End