Registers

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ECE U322Digital Logic Design
Nov. 21, 2005

• Lecture 30
• Synchronous Counters
• FSM Design
• Homework 8 due Thursday, Dec. 1.

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Sequential Circuit Design
Procedure 1. Specify Obtain state diagram or
state table based on problem specification 2.
Write state table if not given in 1 3. Determine
type and number of flip-flops 4. Determine
binary codes for states. 5. Derive flip-flop
input equations. 6. Derive output equations. 7.
Simplify equations from 5 and 6. 8. Draw logic
diagram.
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Counters are FSMs

• Registers that go through a prescribed sequence
  of states upon the application of pulses.
• Design procedure for a synchronous counter is the
  same as with any other synchronous sequential
  circuit.
• In a counter, the output is the state.

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State Diagram for a 4-bit counter
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Binary Counter
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K-maps
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With EN (count enable input), the flip-flop input
equations are JQ0 KQ0 JQ1 KQ1 JQ2 KQ2
JQ3 KQ3 The input equation for flip-flop,
Qi, at any stage for i 1,2, n (n-bit counter)
is JQi KQi
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2-bit Down Counter using J-K flip-flops

• State Diagram

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• State Table
• Present State Input Next State FF-Inputs

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• Input/Output Equations
• Circuit Diagram

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• Timing Diagrams

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Up-Down Counter

• For an Up-Counter
• The input equation for flip-flop, Qi, at any
  stage for i 1,2, n (n-bit counter) is
• JQi KQi
• For a Down-Counter
• The input equation for flip-flop, Qi, at any
  stage for i 1,2, n (n-bit counter) is
• JQi KQi

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4-bit Up-Down Counter
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Arbitrary Count Sequence

• (0,1,3,4,6,7)
• State Diagram

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State Table
What do we do with unused states?
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K-Maps
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Circuit Diagram
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Timing Diagram
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Binary Counter with Parallel Load

• It is often useful to have a parallel load for
  transferring an initial binary number into the
  counter prior to counting.
• When the input load control is equal to 1, it
  disables the count operation and causes a
  transfer of data from the four data inputs into
  the four flip-flops.
• If both control inputs are 0, clock pulses do not
  change the state of the register.

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4-Bit Binary Counter with Parallel Load
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Register with count, load, shift functions

• Design a register that can perform the following
  functions