Registers and Counters

1
Chapter 6
4241 - Digital Logic Design
Registers and Counters
2
Registers

• Group of D Flip-Flops
• Synchronized (Single Clock)
• Store Data

3
Registers
A3
A2
A1
A0
Note New data has to go in with every clock
4
Registers with Parallel Load

• Control Loading the Register with New Data

LD Q(t1)
0 Q(t)
1 D
5
Registers with Parallel Load

• Should we block the Clock to keep the Data?

Delays the Clock
6
Registers with Parallel Load

• Circulate the old data

D
Q
A0
I0
D
Q
A1
I1
A2
D
Q
I2
D
Q
A3
I3
CLK
Load
7
Shift Registers

• 4-Bit Shift Register

SerialInput
SerialOutput
8
Shift Registers
Q3
Q2
Q1
Q0
SI
SO
CLK
Q3
Q2
Q1
Q0
9
Serial Transfer
SI
SO
SI
Shift Register A
Shift Register B
CLK
CLK
10
Serial Addition
SI
ShiftControl
FA
x y z
S C
CLK
Q
D
CLR
Clear
11
Universal Shift Register

• Parallel-in Parallel-out
• Serial-in Serial-out
• Serial-in Parallel-out
• Parallel-in Serial-out

12
Universal Shift Register
S1S0
SI for SL
SI for SR
D1
D0
D2
D3
13
Universal Shift Register
Q3
Q2
Q1
Q0
S1
S0
USR
SRin
SLin
D3
D2
D1
D0
Mode Control Mode Control Register Operation
S1 S0 Register Operation
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load
14
Ripple Counters

• Ripple ? Asynchronous

Q0
Q1
Q2
Q3
15
Ripple Counters
Q3
Q2
Q1
Q0
CLK
0
1
2
3
4
5
6
7
8
9
16
BCD Ripple Counter
17
Decades Counter
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
BCDCounter
BCDCounter
BCDCounter
Count
(CLK)
1s Digit
10s Digit
100s Digit
18
Synchronous Binary Counter
Q3
Q2
Q1
Q0
Enable
CLK
To Next Stage
19
Up-Down Binary Counter
Q3
Q2
Q1
Q0
CLK
Up
Down
20
BCD Counter
0
0
0
0
0
1
1
1
1
0000
0001
0010
0011
0100
1
1
1001
1000
0111
0110
0101
1
1
1
1
0
0
0
0
0
Q3
Q2
Q1
Q0
E
21
BCD Counter
0
0
0
0
0
1
1
1
1
0000 / 0
0001 / 0
0010 / 0
0011 / 0
0100 / 0
1
1
1001 / 1
1000 / 0
0111 / 0
0110 / 0
0101 / 0
1
1
1
1
0
0
0
0
0
Q3
Q2
Q1
Q0
y
E
22
Binary Counter with Parallel Load
Q3
I3
CLR LD Count Q(t1)
0 x x 0
1 0 0 Q(t)
1 0 1 Q(t)1
1 1 x I
Q2
I2
Q1
I1
Q0
I0
LD
Count
CLR
Usually Asynchronous Clear
23
BCD Counter Example
LD
Q3
I3
0
A3
0
Q2
I2
A2
Q1
I1
0
A1
Q0
I0
0
A0
Count
Count
CLR
CLK
1
24
Ring Counter
1000
0001
0010
0100
25
Johnson Counter
0111
0000
0001
0011
1111
1000
1100
1110
26
Homework

• Mano
• Chapter 6
• 6-2
• 6-3
• 6-4
• 6-13
• 6-14
• 6-16
• 6-18

27
Homework
6-2 Include a synchronous clear input to the Register with Parallel Load. The modified register will have a parallel load capability and a synchronous clear capability. The register is cleared synchronously when the clock goes through a positive transition and the clear input is equal to 1.
6-3 What is the difference between serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial. What type of register is needed?
28
Homework
6-4 The content of a 4-bit register is initially 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of the register after each shift?
6-13 Show that a BCD ripple counter can be constructed using a 4-bit binary ripple counter with asynchronous clear and a NAND gate that detects the occurrence of count 1010.
6-14 How many flip-flop will be complemented in a 10-bit binary ripple counter to reach the next count after the following count(a) 1001100111(b) 0011111111(c) 1111111111
29
Homework
6-16 The BCD ripple counter has four flip-flops and 16 states, of which only 10 are used. Analyze the circuit and determine the next state for each of the other six unused states. What will happen if a noise signal sends the circuit to one of the unused states?
6-18 What operation is performed in the up-down counter when both the up and down inputs are enabled? Modify the circuit so that when both inputs are equal to 1, the counter does not change state, but remains in the same count.