An Effective Low Power Design Methodology Based on Interconnect Prediction

1
An Effective Low Power Design Methodology Based
on Interconnect Prediction

• Shih-Hsu Huang (Chung Yuan Christian
  University, Taiwan)
• Mely Chen Chi (Chung Yuan Christian
  University, Taiwan)
• Hsu-Ming Hsiao (Industrial Research Technology
  Institute, Taiwan)

2
Outline

• Introduction
• Motivation
• Interconnect Prediction
• The Proposed Design Flow
• Front-end design procedure
• Back-end design procedure
• Experimental Results on a Test Chip
• Conclusions
• Future Work

3
Introduction

• Low power is a significant concern for the
  todays ASIC designs.
• Power optimization at the logic level
• Power estimation at the logic level
• Typical ASIC design flow
• The major challenge

4
The Demand for Low Power Methodology

• Due to the remarkable success and growth of
  portable personal computing devices and wireless
  communication systems, power consumption is
  becoming increasingly important in the ASIC
  design.
• However, increasing design complexity and higher
  clock frequencies result in higher power
  consumption.

5
Power Estimation at the Logic Level

• The dominant source of power dissipation in CMOS
  circuit is the charging and discharging of the
  node capacitances.
• The power dissipation of a node i
• Pi 1/2 V2 Ci f Ei
• V supply voltage
• Ci node capacitance
• f clock frequency
• Ei switching activity

6
Cost Measure

• The product of Ci and Ei is referred to as the
  switched capacitance.
• At the logic level, it is assumed that V and f
  are fixed, and thus, the total switched
  capacitance of the circuit is assumed to be the
  cost measure that is optimized.

7
Typical ASIC Design Flow

• Many design automation tools have been used
  extensively in the industry.These tools achieve
  very good results in their own stage.
• The switching activities of nodes in a circuit
  are reported by the logic simulator Verilog/PLI.
• Synopsys/Power Compiler may optimize
  simultaneously for timing, area, and power during
  the synthesis stage.

8
Power Optimization
Estimated Wire loads
Switching activities
Power Optimization
9
The Major Challenge

• Since interconnect plays a role in determining
  the total chip power dissipation, the power
  optimization at the logic level may be inaccurate
  due to the lack of place and route information.
• In this paper, we will present an effective low
  power design methodology based on interconnect
  prediction.

10
Motivation

• To shorten the design time, it is very important
  to correctly supply the power optimization
  environment all the related information
• The mismatch between the logic hierarchy and the
  physical hierarchy may cause the estimated wire
  load far away from the correct value.
• The reduction of power is larger, if the
  capacitances of higher switching frequency nets
  are reduced.

11
Basic Ideas

• To speedup the design process.
• Provide accurate wire loads at logic level.
• To minimize the power dissipation of the chip.
• Develop a methodology for effective use of
  existing design automation tools.

12
Our Methodology

• A method to create wire load models.
• A design flow, including front-end design
  procedures and back-end design procedures, to
  select appropriate wire load models during power
  optimization.

13
Practical Wire Load Model

• A wire load model describes wire load value
  according to the fan-out number of a net and the
  physical size of the block encloses the net.
• A wire load model consists of a set of wire load
  tables. Each table contains wire load data such
  as capacitance, resistance, and the average wire
  length for a series number of fan-out.

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Wire Load Table
wire_load (block_size_name) resistance
R_UNIT capacitance C_UNIT slope
S fanout_length(1,L1) fanout_length(2,L2) fa
nout_length(X,Lx)
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The Method to Create Wire Load Models

• Collect physical blocks from many layouts of the
  same processing technology.
• Apply the analysis procedure to every physical
  block.
• Apply the linear regression technique to the data
  and get a family of slopes of different wire load
  tables.

16
The Wire Load Analysis Procedure
17
The Wire Load Data After Linear Regression
18
The Proposed Design Flow

• Front-End Design
• By constructing physical hierarchy during the
  synthesis stage, we can effectively make use of
  the practical wire load model.
• Back-End Design
• In order to shorten the design time, the logic
  hierarchy and the physical hierarchy must be
  consistent.

19
The Advantages of Our Approach

• It constructs physical hierarchy during the
  synthesis stage
• To supply accurate wire loads for power
  optimization
• To speedup the design process
• The final capacitances will be as close to the
  estimated values in the synthesis stage.

20
Front-End Design Procedure

• Construct physical hierarchy during the synthesis
  stage
• enclose high switching activity modules within a
  smaller physical block
• Accurately estimate each physical block size
• fb SCell_Area(Mi)
• Select correct wire load model for each physical
  block
• Perform gate-level power optimization based on
  the estimated wire loads

21
The Front-End Design Flow
22
Logic Hierarchy
23
Physical Hierarchy
TOP
H
G
D E F
C
A B
C
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Synthesis Steps

• Quick Synthesis on each leaf modules
• re-synthesize leaf modules A and B with the
  selected wire load model
• synthesize the module G with the selected wire
  load model
• synthesize the module H with the selected wire
  load model
• synthesize the top module with the global wire
  load model

25
Back-End Design Procedure

• The floorplan must be consistent with the
  physical hierarchy constructed at the synthesis
  stage
• the command group of Avant!/Apollo can be used
  to instantiate logic modules or instances in a
  physical block.

26
The Test Chip

• We used a wireless chip as an example to test the
  effectiveness of the proposed design methodology.
  
• This test chip is implemented using TSMC 0.35µm
  CMOS technology.

27
Clock Gating

• To save power consumption, clock gating is
  implemented.
• When the system is at standby mode, all the gated
  clock in the chip are disabled (i.e., only system
  clock is active). On the other hand, the chip
  will have peak power consumption when 6 clocks
  are active.
• Due to clock gating, we may distinguish design
  instances or logic modules according to their
  clocks.

28
The Clock Gating Structure
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Experimental Results
System Condition chip1 chip2 power reduction
standby_mode 0.162 mA 0.173 mA 6.3
peak power consumption (RAM macros excluded) 3.07 mA 3.12 mA 1.6
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Conclusions

• In this paper, we presented an effective low
  power design methodology. Our goal is to minimize
  the power dissipation and shorten the design time
  at the same time.
• This approach can be easily incorporated into
  existing ASIC design flow.
• Experimental data shows that this approach
  achieved very good results, especially in the
  standby mode power dissipation reduction.

31
Future Work

• We will apply the proposed design methodology to
  more benchmarks to test the effectiveness.