VIRAM1: A MediaOriented Vector Processor with Embedded DRAM

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VIRAM1 A Media-Oriented Vector Processor with
Embedded DRAM

• Computer Science Divison
• University of California, Berkeley

http//iram.cs.berkeley.edu
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VIRAM1 Architecture

• VIRAM1, a Vector microprocessor designed in an
  Intelligent RAM (embedded DRAM) process
• Media-oriented processor
• 64-bit embedded MIPS core
• Custom 256-bit vector datapath
• 13 Megabytes of embedded DRAM

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VIRAM1 Design Overview

• Technology IBM SA-27E
• 0.18mm CMOS
• 6 metal layers (copper)
• 325 mm2 die area
• 230 mm2 for memory/logic
• 8 DRAM banks 160 mm2
• 4 Vector lanes 40 mm2
• Transistor count 125M
• Power supply
• 1.2V logic, 1.8V DRAM
• Peak vector performance
• 1.6/3.2/6.4 Gops wo. multiply-add (64b/32b/16b)
• 2.4/4.8/9.6 Gops w. multiply-add
• 1.6 Gflops (SP)

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VIRAM1 Design Status

• Combination of many design styles
• Embedded DRAM, SRAMs Macros from IBM
• Standard Cell Library From IBM
• Scalar Core Synthesizable Verilog from MIPS
• Vector Control Verilog from Berkeley
• Vector Datapaths Verilog and custom logic design
• Initial Design Completed Summer 2002
• Verification of all components
• Verilog logic Directed and random test using
  custom framework based on VCS over 5M lines of
  code
• Custom design Star-RC/Star-EX netlist
  extraction NanoSim for functional checks, HSpice
  for critical circuits
• Standard cell PR Timing and LVS performed with
  Apollo timing verified with PrimeTime
• Full layout DRC Performed with Hercules
• Verification and Tapeout Completed Late 2002

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VIRAM1 Software Status

• Simulator, assembler previously completed
• VIRAM1 compiler developed from CRAY PDGCS
  vectorizing compiler
• Variety of benchmark applications (EEMBC Embedded
  Applications, DARPA DIS Suite) hand-coded for use
  on simulator and real hardware

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VIRAM1 Hardware Testing

• Hardware testing is based on the MIPS Malta
  development board

• Provides I/O, memory,
• power, etc
• Built-in monitor and
• debugging facility
• Allows full control of
• voltages, clock rates,
• bypassing internal
• blocks (PLL, caches,
• etc)
• Test platform used to
• discover I/O error
• Initial design referenced faulty I/O pad block
  without signal enables
• All functional models have been re-checked and
  updated to correct versions
• Simulations re-run and verified