This file contains a block diagram and some functional notes on the L2Beta 9U card design.

1
This file contains a block diagram and some
functional notes on the L2Beta 9U card
design. Results of discussions among Philippe
Cros, Drew Baden, and Bob Hirosky are merged into
the design. Base design uses an Altera 20K200
FPGA and PLX 9054 PCI interface The choice of the
Altera will expedite our firmware development
cycle. The choice of the PLX chip will give our
design greater flexibility, because the PLX
supports both 3.3V and 5V PCI buses. Use of a
commercial PCI interface will also reduce our
firmware complexity. Details of the mechanical
design are show in talks by Philippe Cros.
2
Overview of FPGA Blocks
P1
VME Block
15
P2
23
TSI MBus Block
P3
62
LBus Block
PLX ADDON
MB_PECL
MB Arb. Block
14
MB TTL
AD dir
TTL 2 PECL
Scaler Block
DA enables
32
ALTERA 20K200 360 (of 272) pins used
MB AD/DA Block
163
MBAD
MBDA
FIFO (18bits x4k)x8
MBDA
15
Config/Spy Block
FIFO Block
36
These blocks have tightly coupled functions
3
Add-on bus block
Fixed by AMCC SPECS
4
VME block
Config./SPY block
P1
GAP
6 signals
GA40
JTAG/EPROM/DIAGNOSTIC I/O, etc
5
TSI MBusscalar block
VME block (signals on P1P2)
P1
MOD_DONE15 EV_LOADED3 START_LOAD DONE_OUT MB_R
ESET AP_FIFO_EMPTY
6 signals
GA50
55 signals
ECL SALERS32
MISC out EV_LOADED30, START_LOAD,
DONE_OUT, MB_RESET, AP_FIFO_EMPTY
6
P3
MB_WR
DDONE
Mbus Arbitration
TTL 2 PECL
14 signals
Open collector MBUS arbitration lines require
output buffers and separate input pins
7
MBUS AD/DA FIFO block
FPGA 188 Pins used
P3
AD_DIR
AD32
OE PIO_OUT
DA128
OE PIO_IN
WCLK, WEN
RCLK,REN,OE
EF,FF
MB DMA AD10
FIFO (18bits x4k)x8
8
Arbitration of shared inputs from Mbus to FPGA
DEFAULT settings AD_DIR 0 (input
mode) PIO_OE_INPIO_OE_OUTFIFO_OE0
BROADCAST DATA IN FIFO WEN set (PIO OEs
deasserted) by address decode FIFO WCLK WEN
DSTROBE (New address sets FIFO_IN bits to flag
BOE) PIO DATA IN (TARGET MODE) OE_PIO_IN set
(OE_PIO_OUT, FIFO_OE deasserted AD_DIR0) by
address decode Data/Address latched in FPGA at
DSTROBE, DDONE pulsed PIO DATA OUT (TARGET
MODE) OE_PIO_OUT set (OE_PIO_IN, FIFO_OE
deasserted, AD_DIR0) by address decode Address
latched in FPGA on DSTROBE/RW DATA fetched,
placed on MBUS, DDONE pulsed PIO DATA OUT
(MASTER MODE) Boss Requested OE_PIO_OUT set
(OE_PIO_IN, FIFO_OE deasserted, AD_DIR1) AD/DATA
placed on MBUS, WR set, DSTROBE pulsed DDONE
received, OE_PIO_OUT deasserted, AD_DIR0 PIO
DATA IN (MASTER MODE) Boss Requested OE_PIO_IN
set (OE_PIO_OUT, FIFO_OE deasserted,
AD_DIR1) ADDR placed on MBUS, WR set, DSTROBE
set DDONE received, Data Latched in FPGA,
OE_PIO_INDSTROBE deasserted,AD_DIR0
9

• Comments
• Explicit CDF compatibility is not implemented in
  this draft
• The FIFO outputs share the same FPGA I/O pins as
  PIO, FIFO readout is simplified, because its
  done in 128 bit words
• Spare bits in the FIFOs are used to tag
  beginning and possibly end of a data source, this
  can simplify DMA firmware
• Utility features include LA hookups to FPGA,
  LEDS, and switches
• 16 free I/O pins are still available in this
  configuration, additional pins could easily be
  made available by
• Adding external logic to MBUS Arbitration (5)
• Reducing FIFO special bits (2)
• Reducing LA/LED/Switch bits (10)
• POSSIBLE FREE PINS w/ minimal impact on design
  33
• Uses for additional I/O pins (and pins needed for
  each function)
• Provide compatibility w/ a custom designed
  64-bit interface (12-16 pins)
• Provide compatibility w/ a 64-bit PCI local bus
  (40 pins)

10
Additional Comments More pins may be freed
up by using 32 bits to ECL drives as LA bits.
A front panel redefine these line to be LA lines,
instead of scalar lines for diagnostic testing.
This would leave us with more than 40 free I/O
pins in the design proposed here.