PowerPointPrsentation

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2. Sensor technology
Silicon wafers Properties of thin films Physical
vapour deposition Evaporation Sputtering Struct
ure of films Chemical vapour deposition Plasma
enhanced deposition LPCVD Oxidation Si Doping
Photolithography Etching DRIE etching Bulk
micromachining Anisotripic etching
Process of a thermopile
Version 4.10.2007
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The silicon wafer Wafers are monocrystals from
silicon, mainly made for microelectronic device
production Si has a cubic crystal lattice. For
alcalic solution, the (111) plane is an etchstop
plane Diameter 4 and 6 inch Microsystems 8
inch to 12 inch Microelectronics Large crystals
are grown. Wafers are cut from them and
polished. The way they are cut is given by the
surface plane (100), (110),(111) and the flat.
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Thin films Thickness 20 nm to 2 µm Clean room
needed (dust particles larger than film
thickness) Application Electronics,
sensors Optics, antireflection coatings Decoration
, gold plating Tribology, hard coatings Packaging
for food
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General properties Thin films contain voids and
trace atoms (e.g. Argon, Hydrogen) ? Internal
structure Crystallites, columnar, porous ?
Density smaller than for bulk material Surface
effects important ? Resistivity greater than
bulk ? Temperature coefficient (TCR) smaller than
bulk
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Stress in thin films Extremely high stress level
possible Silicon Nitride up to 1,2 GPa (steel
would brake!)
Compression Membranes buckle Tension Cracks,
delamination, membranes brake
Origin - Thermal - Bonds too long or too
short - Crystallites want to grow and fight for
space
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PVD Evaporation PVD Physical Vapour
Deposition Evaporation of a metal in
vacuum Thermal or e-gun Easy to do Poor film
quality Used for - Exotic materials - Laboratory
experiments
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PVD Sputtering
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PVD Sputtering Argon gas electric field ?
Plasma Accelerated Ar ions hit target (e.g. plate
of gold) and remove Au atoms Au atoms deposit on
surface of substrate Pro higher energy of
adsorbed atom Pro (?) Control of many
parameters Contra Complicated machine Contra
Targets are expensive
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Thin film growth - Particle hits surface -
Particle walks around and looks for a place -
Particle comes to rest
Source S. Wolf, N. Tauber Silicon Processing
for the VLSI era
Important parameters - Energy of particle
Thermal 0,2 eV, Sputtering 4-40 eV - Temperature
of substrate
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Morphology of thin films 3-Zone model of Movchan
and Demchisin Parameter TS/ TM Temperature of
substrate / Melting point
0,25 0,45 TS/ TM
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Morphology of thin films Zone 1 TS/ TM lt 0,25.
No surface mobility, few nuclei, dentrites and
shadowing, adhesion bad, porosity Zone 2 0,25 lt
TS/ TM lt 0,45. Surface mobility, voids fill up,
columnar structure, better adhesion Zone 3
0,45 lt TS/ TM. Volume diffusion,
recrystallisation Problem of evaporation Zone 3
often not accessible since melting point too
high Sputtering Higher energy moves transition
to lower temperature
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CVD Chemical vapour deposition For insulators
and for silicon films The material is delivered
as a gas. A chemical reaction takes place, one
product is deposited as a solid, the other is a
gas and is pumped away. Example Silicon nitride
(Si3N4) thin films 3 SiH4 4 NH3 ? Si3N4
12H2 How is the reaction initiated - High T
LPCVD (Low pressure CVD) impotant in Si
technology - Plasma enhanced PECVD
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PECVD Plasma deposition
P 10-500 Pa T 250C - 400C Used for Si
nitride Si3N4 Si oxide SiO2 Si carbide SiC
Kathode Plasma Substrate Heater Anode
Pump Gas supply
Hydrogen incorporated in films Compressive
stress, goes to tensile by annealing when the H
is removed. Pinholes and voids, poor step coverage
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• High Temperature processes
• Si stands 1200C
• ?High T processes ok ?Solid state diffusion
  possible
• ?Special furnaces needed
• Furnaces must be
• Made of quarz
• Kept extremely clean (diffusion!)
• Large (T-gradient) ?Batches with 20 to 50 wafers

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Si furnace 3 zone furnace Several tubes for
different processes
Gas supply 3 zone furnace Vacuum and
exhaust
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Si furnace
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LPCVD Low pressure chemical vapour deposition p
100 ... 100 Pa, T 600C to 750C Very good step
coverage Si nitride 3SiH4 4NH3 ? Si3N4
12H2 Very high tensile stress Si oxide SiH4
O2? SiO2 2H2 Silicon deposition
(polycrystalline) SiH4 ? Si 2H2 Core
processes of microelectronics!
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Thermal oxidation Si oxide is a good insulator Si
O2 ? Si O2 800C to 1200C, dry
oxidation Process slow, rate decreases with film
thickness due to diffusion limitation Si 2H2O
? Si O2 2H2 Wet oxidation, faster, 900C to
1100C. Water from the burning of H2 and O2
(purer than liquid water).
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Overview on Thin film deposition
PVD Physical Vapour Depositon
CVD Chemical Vapour Depositon
Evaporation
Sputtering
LPCVD Low Pressure CVD (High T)
PECVD Plasma enhanced CVD (Low T)
Metals
Insulators, Polysilicon
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Doping Small amount of dopants change the
electrical behaviour essentially p-doping
Boron n-doping Phosphorous Almost pure
(intrinsic) 1000 ?cm Low doping gt1
?cm Electronics, Piezoelectic and
thermoelectric sensors Medium
doping 1...0,01 ?cm High doping 0,01 ?cm Ohmic
contacts Metallic degeneration ltlt0,01 ?cm
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• How to do doping
• During crystal growth or deposition
• Diffusion from
• Gases in the furnace
• Solid source in the furnace
• Thin films
• Implantation of high energy ions
• Local doping is done using a mask during the
  doping process

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Lithography Thin film process - Deposit film -
Cover with photoresist - Expose UV light through
mask - Develop - Etch - Remove resits - Deposit
next thin film
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Photoresist - Photosensitive polymer - No shrink
or swelling - Resistant against etching -
Removable Components 1. Solvent 2. Resin Makes
matrix, not photosensitive 3. Inhibitor
Photoactive Deposition Spin on rotating
substrate
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Masks and alignment Quarz glass with Cr thin
film Structured by E-beam, pattern generator or
with an optically reduced recticle Mask aligner
Mask vs substrate movable in x,y and angle 20 µm
gap (proximity alignment) Optical alignment
marks
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Proximity aligner
UV radiation
Less effort than focussing Gap about 20 µm Full
wafer Allows 2 µm structures Standard in thin
film technology
Glass mask Cr Resist Thin film Substrate
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Alignment crosses
Casette to casette possible Light slit some
µm Each layer fits in the marks of the previous
one
Perfect alignment
Misalignment some µm
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Resolution of optical lithography Thin film
technology has structures with 1 or 2µm VLSI
need lt1µm Deep UV Not proximity alignment, but -
Contact - Optical focussing of mask on substrate
allows structures of 50 nm
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Lithography full process - Clean and dry
substrate - Expose to HMDS to increase adhesion -
Spin on resist - Softbake 90 - Align and
expose - Develop, rinse and dry - Postbake 180
(optional) - Etch - Strip resist in aceton or in
oxygen plasma
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Lithography alternatives
Developing Etching Stripping
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Etching of thin films Etching Removing the
surface of a solid body by chemical reaction
(desolving) or by particles with high energy
(sputtering) Etch rate R Removed thickness /
time Selectivity S R1 / R2 Mask - Film Film
- Substrate Film 1 - Film 2 Overetching Overe
tching results in poor process control Example
meander resistor 10 µm width, R1000 ? 9 µm
width R1110 ? 8 µm width R1250 ?
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Anisotropic etching Etch rate depends on
direction Anisotropy E.g. fast vertical etching,
slow lateral etching vertical walls
Factor of Anisotropy Rl lateral Rate Rv
vertical Rate
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Chemical vs physical etching
Pure sputter etching is very rarely used.
Advanced dry etching Chemical component
physical component
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Dry etching

• Plasma and substrate in two different places.
• Chemical etch by reactive radicals
• Very selective
• Isotropic
• Many wafers in a batch
• Application Stripping resist in oxygen plasma

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Plasma etching (PE)

• Subtrate in the plasma
• Low throughput
• Physical component can be tuned from low to high
  by voltage

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Plasma etching (PE)

• Al structures on silicon
• Deposit and structure Al
• Etch Si by PE isotropically with high selectivity
  vs Al

C. Lindner et al., Transducers 1991, p. 524
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Structuring Si by RIE (reactive ion etching)

Chemical attack by reactive species Physical
attack by fast ions Facetting Eroded
trenches Combined attack Sidewall passivation
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RIE processes

• Low pressure (1 Pa) allows long free path, large
  acceleration length and large momentum
• AC DC, substrate becomes negatively loaded
• Etching and deposition of sidewall passivation
  simultaneously
• Switching back and forth between etching and
  passivation
• Best aspect ratio, but scalloping (ripples on
  the sidewall)
• E.g. Bosch RIE process

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Bulk micromachining 3 dimensional structures
are made by removing parts of the wafer (bulk
material) E.g. etching away the Si below a
membrane Wet chemical anisotropic etching in KOH
solution The (111) plane of Si is almost not
etched Etchstop plane Note the convention
(plane) and ltdirectiongt The (100) plane is the
plane perpendicular to the lt100gt direction
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Etchstop plane Etch rates R(111)R(100) ?
1100 The angle of 55 is the angle between a
side and a volume diagonal of a
cube. http//attila.stevens-tech.edu/rbesser/ChE_
702/Lecture_Handout/Bulk_Micro.pdf
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Thermopile process
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Thermopile Technology

• Depo PECVD nitride (passivation) (d)
• Litho III open bond pad
• Etch nitride open bondpads
• Litho IV (Back) Open layers as DRIE etch mask
• Etch oxide
• Etch DRIE (e)
• Saw
• Depo IR absorbing layer
• Mount on housing
• Wire bond
• Close housing

• Material Si (100)
• Depo Thermal oxide
• Depo LPCVD nitride (a)
• Depo LPCVD polysilicon
• Litho I polysilicon
• Etch polysilicon (RIE) (b)
• Depo Sputtering Al
• Litho II Al
• Etch AL plasma (c)

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Thermopile process integration compatibility of
steps