Simulation of Switching Converters

1
Chapter 9

• Simulation of Switching Converters

2
Overview

• PSpice
• PSpice Simulations using .CIR
• PSpice Simulations using schematics entry
• PSpice Simulations Using Behavioral Modeling
• PSpice simulations using vendor models
• Small-signal analysis of switching converters
• Creating capture symbols for PSpice simulation
• Solving convergence problems
• Matlab
• Simulink

3
PSpice Simulations using .CIR
An Ideal Open-Loop Buck Converter
Open-loop buck converter simulation SWITCHING
FREQUENCY 1 KHZ DUTY CYCLE 50 VPWM 1 0
PULSE(0 10 0 1US 1US 0.5MS 1MS) PULSE PWM
SOURCE PULSED VOLTAGE 10 V, RISE TIME 1 US,
FALL TIME 1 US, PULSE WIDTH 500 US,
PERIOD 1 MS. L0 1 2 10M C0 2 0 100U RL 2 0
5 .TRAN 50US 20MS .OPTION ITL50 .PROBE .END
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PSpice Simulations using .CIR
An Ideal Open-Loop Buck Converter
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PSpice Simulations using .CIR
An Ideal Open-Loop Buck Converter
L 50 mH
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PSpice Simulations using .CIR
An Ideal Open-Loop Buck Converter
L 5 mH
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PSpice Simulations using .CIR
An Ideal Open-Loop Buck Converter
L 1.25 mH
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PSpice Simulations using .CIR
An Ideal Open-Loop Buck Converter
L 10 mH and C 500 uF
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PSpice Simulations using .CIR
An Ideal Open-Loop Buck Converter
L 1.25 mH and C 500 uF
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PSpice Simulations using .CIR
Voltage-controlled switch
Sltnamegt N N- NC NC- SNAME .MODEL SNAME VSWITCH
(RON0.01 ROFF1E7 VON0.7 VOFF0)
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PSpice Simulations using .CIR
Current-controlled switch
Wltnamegt N N- VN WNAME .MODEL WNAME ISWITCH
(RON0.01 ROFF1E7 ION0.1 IOFF0)
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PSpice Simulations using .CIR
Buck Converter with an Ideal Switch
OPEN-LOOP BUCK CONVERTER WITH AN IDEAL SWITCH
SWITCHING FREQUENCY 1 KHZ DUTY CYCLE 50 VS
1 0 10.0 VPWM 100 101 PULSE(0 1 0 1US 1US 500US
1MS) S1 1 2 100 101 SX RSX 100 0 10G DFW 0 2
D1 L0 2 3 10M C0 3 0 100U RL 3 0 5 .MODEL SX
VSWITCH (RON0.01 ROFF1E7 VON1 VOFF0) .MODEL
D1 D .TRAN 0.05MS 20MS .PROBE .END
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PSpice Simulations using .CIR
Buck Converter with an Ideal Switch
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PSpice Simulations using .CIR
Buck Converter with an Ideal Switch
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PSpice Simulations using .CIR
Using Initial Conditions IC
L0 2 3 100U IC1 C0 3 0 IC5 .TRAN 2NS 200NS UIC
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PSpice Simulations using schematics entry
Boost converter
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PSpice Simulations using schematics entry
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PSpice Simulations using schematics entry
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PSpice Simulations Using Behavioral Modeling

• ABM.OLB part library
• Control system parts

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Control system parts
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Control system parts
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Control system parts
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Control system parts
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Control system parts
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PSpice-equivalent parts
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PSpice-equivalent parts
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Operators in ABM expressions
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Operators in ABM expressions
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Functions in arithmetic expressions
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Functions in arithmetic expressions
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Examples of ABM blocks use
ABM and PARAM
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Examples of ABM blocks use
Node voltages can be accessed from ABM blocks
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Examples of ABM blocks use
RMS meter
If(argument,then,else)
If (TIMElt0, 0, SQRT(SDT(PWR(V(IN),2))/TIME))
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Examples of ABM blocks use
PWM modulator
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Examples of ABM blocks use
VCO implementation with ABM1
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PSpice Simulations Using Control Blocks
PWM modulator with control blocks
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PSpice Simulations Using Control Blocks
Model of an operational amplifier
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PSpice Simulations Using Control Blocks
Open loop frequency response
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PSpice Simulations Using Control Blocks
Closed loop amplifier
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PSpice Simulations Using Control Blocks
Closed loop frequency response
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Voltage mode PWM boost converter
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Voltage mode PWM boost converter
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PSpice simulations using vendor models
.TRAN 0 30m 0 0.1u .OPTIONS STEPGMIN .OPTIONS
ABSTOL 10p .OPTIONS ITL1 400 .OPTIONS ITL4
500 .OPTIONS RELTOL 0.01 .OPTIONS VNTOL 10u
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PSpice simulations using vendor models
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Vorperian models for PSpice
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Vorperian models for PSpice
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Vorperian models for PSpice
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Vorperian models for PSpice
VMSSCCM Small signal continuous
conduction voltage mode model Params RMPHITE
--gt External ramp height D --gt
Duty cycle Ic --gt Current flowing
from terminal C Vap --gt Voltage
across terminal A P Rsw --gt Switch
on resistance Rd --gt diode on
resistance Rm --gt which models the
base storage effects Re --gt models
ripple across esr of cap Pins control voltage
-- common --------
passive----- active --
.subckt VMSSCCM A P C VC Params RMPHITE2
D0.4 IC1 VAP20
Rsw1e-6 Rd1e-6 Re1e-6 Rm1e-6 efm 4 0
value v(Vc)/rmphite e2 A 6
valuev(0,4)Vap/d g1 A P valuev(4)IC
gxfr 6 P VALUEI(vms)D exfr 9 P
VALUEV(6,P)D vms 9 8 0 rd 8 C
drd(1-d)rswd(1-d)rerm rope 4 0 1g
rgnd 0 P 1g .ends
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Small-signal analysis of switching converters
Small-signal AC analysis
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Small-signal analysis of switching converters
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Small-signal analysis of switching converters
Open-loop transfer function
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Small-signal analysis of switching converters
Input impedance
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Small-signal analysis of switching converters
Input impedance
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Small-signal analysis of switching converters
Output impedance
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Small-signal analysis of switching converters
Output impedance
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Small-signal analysis of switching converters
Small-signal transient analysis
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Small-signal analysis of switching converters
Small-signal transient analysis
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Averaged-inductor model for a voltage-mode boost
converter
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Output voltage obtained with the
averaged-inductor model
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Measuring the loop gain
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Measuring the loop gain
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Frequency compensation
choose f1 100 Hz for a switching frequency of 1
kHz
PID compensation
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PID compensation
Mag_comp_f1 -7.0985 Ph_comp 32 k1_db
-24.6094 k1 0.0588 k2_db -5.0259 k2
0.5607 R2 588.2076 R3 269.7258 C1
5.0034e-005 C2 1.3496e-006 C3 2.8658e-006
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Boost switching converter with PID compensator
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Simulation results with a PID compensator
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PI compensation
Small-signal model of the boost converter with PI
compensation
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PI compensation
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PI compensation using ABM blocks
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Simulation results of the PI compensation using
ABM blocks
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PI compensation using vendor models
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Simulation results of the PI compensation using
vendor models
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PI compensation using vendor models
Analysis directives .TRAN 0 30m 0 10n SKIPBP
.OPTIONS STEPGMIN .OPTIONS PREORDER .OPTIONS
ABSTOL 10.0p .OPTIONS CHGTOL 0.1p .OPTIONS
ITL2 200 .OPTIONS ITL4 400 .OPTIONS RELTOL
0.01 .OPTIONS VNTOL 10.0u
I/O ERROR -- Probe file size exceeds
2000000000 JOB ABORTED TOTAL JOB TIME
912.11
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Creating capture symbols for PSpice simulation

• Vendors often provide PSpice models for their
  circuit components. They are normally provided
  in a text file with extension .LIB if the file
  has a different extension, it should be changed
  to .LIB
• Start the PSpice Model Editor and from the File
  menu, choose Create Parts
• Browse to find the input model library (.LIB
  file) and click OK to start
• This step creates an .OBL file with a schematic
  symbol linked to your model
• To place the new part into the schematic, open
  Capture, and from the Place menu choose Part.
  Click Add library, then find and add the new
  .OLB file

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Solving convergence problems

• PSpice uses the Newton-Raphson algorithm to solve
  the nonlinear equations in these analyses
• The algorithm is guaranteed to converge only if
  the analysis is started close to the solution
• If the initial guess is far away from the
  solution, this may cause a convergence failure or
  even a false convergence
• If the node voltages do not settle down within a
  certain number of iterations, an error message
  will be issued

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DC analysis error messages

• The DC Analysis calculates the small-signal bias
  points before starting the AC analysis or the
  initial transient solution for the transient
  analysis
• Solutions to the DC analysis may fail to converge
  because of incorrect initial voltage guesses,
  model discontinuities, unstable or bistable
  operation, or unrealistic circuit impedances
• When an error is found during the DC analysis,
  SPICE will then terminate the run because both
  the AC and transient analyses require an initial
  stable operating point in order to start

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DC analysis error messages

• No convergence in DC analysis
• PIVTOL Error
• Singular Matrix
• Gmin/Source Stepping Failed
• No Convergence in DC analysis at Step xxx

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Transient analysis error messages

• If the node voltages do not settle down, the time
  step is reduced and SPICE tries again to
  determine the node voltages
• If the time step is reduced beyond a certain
  fraction of the total analysis time, the
  transient analysis will issue an error message
  Time step too small and the analysis will be
  halted
• Transient analysis failures are usually due to
  model discontinuities or unrealistic circuit,
  source, or parasitic modeling

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Solutions to convergence problems

• There are two ways to solve convergence problems
• the first only tries to fix the symptoms by
  adjusting the simulator options
• while the other attacks the root cause of the
  convergence problems
• Once the circuit is properly modeled, many of the
  modifications of the "options" parameters will no
  longer be required
• It should be noted that solutions involving
  simulation options may simply mask the underlying
  circuit instabilities

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Bias point (DC) convergence

• Checking circuit topology and connectivity
• Modeling of circuit components
• PSpice options are checked to ensure that they
  are properly defined

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Checking circuit topology and connectivity

• Make sure that all of the circuit connections are
  valid
• Check for incorrect node numbering or dangling
  nodes
• Verify component polarity
• Check for syntax mistakes
• Make sure that the correct PSpice units (i.e. MEG
  for 1E6, not M, which means mili in simulations)
  are used

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• Make sure that there is a DC path from every node
  to ground
• Make sure that there are at least two connections
  at every node
• Make sure that capacitors and/or current sources
  are not connected in series
• Make sure that no (groups of) nodes are isolated
  from ground by current sources and/or capacitors
  
• Make sure that there are no loops of inductors
  and/or voltage sources only

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• Place the ground (node 0) somewhere in the
  circuit
• Be careful when floating grounds (e.g., chassis
  ground) are used a large resistor should be
  connected from the floating node to ground. All
  nodes will be reported as floating if "0 ground"
  is not used
• Make sure that voltage/current generators use
  realistic values, and verify that the syntax is
  correct
• Make sure that dependent source gains are
  correct, and that E/G element expressions are
  reasonable

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• Verify that division by zero or LOG(0) cannot
  occur
• Voltages and currents in PSpice are limited to
  the range /- 1e10
• Avoid using digital components, unless really
  necessary
• Initialize the digital nodes with valid digital
  values
• Avoid situations where an ideal current source
  delivers current into a reverse-biased p-n
  junction without a shunt resistance

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Setting up the options for the analog simulation

• Increase ITL1 to 400
• Use NODESETs to set node voltages to the nearest
  reasonable guess at their DC values
• Enable the GMIN stepping algorithm
• Set PREORDER in Simulation Profiles options
• Setting the value of ABSTOL to 1 µ
• PSpice does not always converge when relaxed
  tolerances are used
• Setting GMIN to a value between 1n and 10n will
  often solve convergence problems
• Setting GMIN to a value, which is greater than
  10n, may cause convergence problems

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Transient convergence

• The transient analysis can fail to complete if
  the time step becomes too small
• This can be due to either
• (a) the Newton-Raphson iterations would not
  converge even for the smallest time step size
• (b) something in the circuit is moving faster
  than can be accommodated by the minimum step size

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Transient convergence

• The circuit topology and connectivity should
  first be checked
• Followed by the PSpice options

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Circuit topology and connectivity

• Avoid using digital components, unless really
  necessary
• Initialize the nodes with valid digital value to
  ensure there are no ambiguous states
• Use RC snubbers around diodes
• Add Capacitance for all semiconductor junctions

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Circuit topology and connectivity

• Add realistic circuit and element parasitics
• It is important that switching times be nonzero
• It is recommended that all inductors have a
  parallel resistor
• Look for waveforms that transition vertically (up
  or down) at the point during which the analysis
  halts

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Circuit topology and connectivity

• Increase the rise/fall times of the PULSE sources
  
• Ensure that there is no unreasonably large
  capacitor or inductor

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PSpice options

• Set RELTOL.01
• Reduce the accuracy of ABSTOL/VNTOL if
  current/voltage levels allow it
• ABSTOL and VNTOL should be set to about 8 orders
  of magnitude below the level of the maximum
  voltage and current
• Increase ITL4, but no more than 100

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PSpice options

• Skipping the bias point is not recommended
• Any applicable .IC and IC initial conditions
  statements should be added to assist in the
  initial stages of the transient analysis

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Switching converter simulation using Matlab
Working with transfer functions
Consider a buck converter designed to operate in
the continuous conduction mode having the
following parameters R 4?, L 1.330 mH, C
94 µf, Vs 42 V, Va 12 V
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Switching converter simulation using Matlab
this is a comment parameters R 4 L 1.330
e-3 Rind 100 e-3 C 94 e-6 Resr 10 e-3 Vs
42 Va 12 DVa/Vs Kd Vs/(1-D)2 Sz11/(Re
srC) Req R-(ResrR/(ResrR)) Sz2
(1/L)(1-D)2 Req Rind/L Re(ResrR)/(
ResrR) Wo (1/sqrt(LC)) sqrt((RindreD(1-
D))/(ResrR)) Q Wo/(((Rindre(1-D))/L)(1/(C
(ResrR))))
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Switching converter simulation using Matlab
polynomials are entered in descending order of
S. n11/Sz1 1 n2-1/Sz2 1 NUMconv(n1,n2)
the convolution realizes the product of 2
polynomials define denumerator DEN 1/(Wo2)
1/(WoQ) 1 create TF variable sysTF Kd
tf(NUM,DEN) which returns Transfer function
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Switching converter simulation using Matlab
The location of the poles can be found
using poles roots(DEN) and the frequency
response can be plotted using bode(sysTF)
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Switching converter simulation using Matlab
The small signal transient step response can be
plotted using Figure this command opens a new
figure window step(sysTF)
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Switching converter simulation using Matlab
Working with matrices
Consider a buck converter designed to operate in
the continuous conduction mode having the
following parameters R 4?, L 1.330 mH, C
94 µf, Vs 42 V, Va 12 V.
state-space averaged model of a Buck
converter Rload 4 load resistance L
1.330e-3 inductance cap94.e-6
capacitance Ts1.e-4 switching period Vs42
input DC voltage Vref12 desired output
voltage The average duty cycle is DVref/(Vs)
ideal duty cycle
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Switching converter simulation using Matlab
A 0 -1/L 1/cap
-1/(Rloadcap) B1 1/L 0
during Ton B2 0 0 during
Toff BB1DB2(1-D) C0 1
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Switching converter simulation using Matlab
OLpoles eig(A)
sysOLss(A,B,C,0) step(sysOL)
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Switching converter simulation using Matlab
gamma Vs/L 0
closed-loop poles P1e3-0.3298 0.10i
-0.3298 - 0.10i'
Bf gamma(D/Vref) Fplace(A,Bf ,P)
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Switching converter simulation using Simulink
NUM,DEN TFDATA(sysTF,v)
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Switching converter simulation using Simulink
sysZPK zpk(sysTF)
zeroes -1.0638e006 1455 poles -2657
-76.6 gain -0.010821
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Switching converter simulation using Simulink