Practical Priority Contention Resolution for Slotted Optical Burst Switching Networks

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Practical Priority Contention Resolution for
Slotted Optical Burst Switching Networks
Farid FarahmandThe University of Texas at
Dallas
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Overview

• OBS Overview
• Major issues in OBS
• Switch node architecture of the OBS
• Hardware prototyping of the scheduler unit
• Hardware simulation results

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Optical Burst Switching (OBS)

• Assemble IP packets into data bursts
• Transmit bursts following their headers by an
  offset
• Separated in space and time
• Headers are processed electronically
• Data bursts are passed through the optical
  switches

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OBS Switching Issues

• Burst scheduling scheme
• Channel selection and reservation for the
  arriving data burst
• First-Fit
• Latest Available Unscheduled (with and without
  Void Filling)
• Contention resolution technique
• Resolution of contention between data bursts
• Buffering
• Deflection routing
• Wavelength conversion
• Burst dropping

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OBS Switching Issues

• Burst transmission schemes
• Slotted Bursts are transmitted on slot
  boundaries
• Unslotted Bursts can be transmitted at any time

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Switch Node Architecture
BHP PROCESSOR
SCHEDULER
DEMUX/MUX
and Phase Alignment
Switch Fabric
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Hardware Implementation of the Control Packet
Processor

• Fast processing time
• Must be fast
• Minimize software
• Scalable with a generic design
• Can be used for any burst reservation scheme
• Low cost
• Implementable in an off-the-shelf programmable
  component (FPGA)

Our main emphases Practical approach to
designing the Control Packet Processor
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Control Packet Processor Architecture

• Architectures
• Centralized
• Distributed
• Centralized architecture
• Similar to input queuing
• Single scheduler

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Control Packet Processor Architecture

• Distributed architecture
• Similar to virtual output queuing
• Parallel scheduling
• One per destination
• Advantages
• Minimizing head-of-queue blocking
• Higher reliability
• Allowing concurrent scheduling
• Disadvantage
• High memory requirement
• Each Destination Queue must be sized for the
  worst case

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Scheduling Mechanisms in the Scheduler Block

• Scheduling mechanism
• Latest Available Unscheduled
• Contention resolution technique
• Latest Drop Policy (LDP)
• With offset-time-based QoS
• Shortest Drop Policy (SDP)
• Supports unlimited service differentiation
• Performs better than the Latest Drop Policy

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Comparing SDP and LDP Performance

• Single switch with 4 edge nodes
• Each port has 4 channels
• Full utilization of wavelength converters
• Max data burst duration is 20 slots /
  Exponentially distributed
• 3 levels of service differentiation
• Performance metric Burst Loss Rate (BLR)

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Hardware Prototyping of the Control Packet
Processor

• Basic assumptions
• Slotted transmission of BHPs
• Shortest Drop Policy (SDP)
• Parallel scheduling
• Receiver Block
• All BHP are verified for correct parity and
  framing
• Each request is reformatted, time stamped, and
  passed on to the proper Destination queue
• Destination Queues
• Scheduler

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Hardware Prototyping of the Scheduler

• Arbiter
• Scheduler Core Section
• Processor
• Channel Manager
• Update Switch Setup
• Statistics Accumulator

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Hardware Prototyping of the Scheduler
P inputs along with the counter signal
Flow Control QoS control
If reservation was successful regenerate BHP
One per channel
Checks Start and End times Reserve Requests
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Illustration of the Scheduler Operation

• Three Channels
• Assuming all Channel Queues are empty initially

B1
B2
B3
B4
B5
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Scheduler Prototype

• Implemented on Altera EP20k400E FPGA
• 2.5 million gates
• Maximum clock rate of 840 MHZ
• Core section modeled by Celoxica DK design suite
• Initially modeled using C-language
• Modified into Handel-C language
• Compiled and translated into a gate level VHDL
  code
• Other blocks were designed using VHDL code
• Tested, verified, and synthesized
• Cadance (NcSim)
• Quartus II

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Hardware Simulation Results
Number of clock cycles required to processes
packets in the Destination Queue
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Hardware Simulation Results
Number of NAND gates requires to design the
scheduler unit
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So in Conclusion

• A key issue in implementing the OBS is designing
  a fast and efficient BHP processor
• We presented alternative architectures for the
  BHP packet processor
• We discussed several scheduling algorithms and
  their performance
• We presented hardware results in terms of the
  cost and scalability

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So in Conclusion
Interested? Looking for something to do? or
just Curious?
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End of Slides!
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Practical Priority Contention Resolution for
Slotted Optical Burst Switching Networks
Farid Farahmand, Vinod M. Vokkarane, Jason P. Jue
The University of Texas at Dallas
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Control Packet Processor Architecture

• Architectures
• Centralized
• Distributed
• Centralized architecture
• Similar to input queuing
• All BHP are verified for correct parity and
  framing
• Single scheduler
• Each request is time stamped

RX BLOCK
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OBS Switching Issues

• Burst transmission schemes
• Slotted Bursts are transmitted on slot
  boundaries
• Unslotted Bursts can be transmitted at any time
• Simpler to implement
• ?????Higher loss (due to unpredictable burst
  characterization)

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So in Conclusion

• A key issue in implementing the OBS is designing
  a fast and efficient BHP processor
• We presented alternative architectures for the
  BHP packet processor
• We discussed several scheduling algorithms and
  their performance
• We presented hardware results in terms of the
  cost and scalability