VerilogI

1
Verilog-I

• Ajai Jain (ajain_at_iitk.ac.in)
• Rajat Moona (moona_at_iitk.ac.in)

2
Hardware Description

• Why do we need them?
• To verify the design
• To programmatically generate the circuit (as
  collection of gates) aka synthesis.
• What is important?
• Basically the designs are based on digital
  circuits.
• Digital signals have values 0, 1 (as input)
• Output values are (0, 1, Z)
• Z is a state rather than the value.
• For simulations/verifications, it is required to
  catch errors due to non-assignments.
• X state for the output. X value for the input.

3
A Half Adder

• Inputs A, B
• Output S, C
• Combinatorial circuit
• module HalfAdder(A, B, S, C)
• input A, B
• output S, C
• always _at_(A or B)
• begin
• S A B
• C A B
• end
• endmodule

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Full Adder

• Inputs A, B, C_in
• Output S, C_out
• module FA(A, B, C_in, S, C_out)
• input A, B, C_in
• output S, C_out
• always _at_(A or B or C_in)
• C_out, S A B C_in
• endmodule

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4-bit Adder

• module FourBitAdder(A, B, Cin, S, Cout)
• input 30 A, B
• input Cin
• output 30 S
• output Cout
• always _at_(A or B or Cin)
• Cout, S A B Cin
• endmodule

6
Alternate 4-bit Adder

• module FourBitAdder(A, B, Cin, S, Cout)
• input 30 A, B
• input Cin
• output 30 S
• output Cout
• wire c1, c2, c3
• FA fa0(.A(A0),.B(B0),.C_in(Cin),.C_out(c1)),
• fa1(.A(A1),.B(B1),.C_in(c1),.C_out(c2)),
• fa2(.A(A2),.B(B2),.C_in(c2),.C_out(c3)),
• fa3(.A(A3),.B(B3),.C_in(c3),.C_out(Cout))
• endmodule

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Alternate 4-bit Adder

• module FourBitAdder(A, B, Cin, S, Cout)
• input 30 A, B
• input Cin
• output 30 S
• output Cout
• wire c1, c2, c3
• FA fa0(A0,B0,Cin,S0,c1)
• FA fa1(A1,B1,c1,S1,c2)
• FA fa2(A2,B2,c2,S2,c3)
• FA fa3(A3,B3,c3,S3,Cout)
• endmodule

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Signals

• Two types of signals
• Wire (Have no state)
• Reg (State)
• A combinatorial circuit can be realized
  completely by just wire kind of signals.
• Register signals are used primarily for
  sequential circuits

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Latch revisited

• module latch(le, d, r, s, q)
• input le, d, r, s
• output q
• reg q
• always _at_(le or d or r or s) begin
• if (r) q 1b0
• else if (s) q 1b1
• else if (le) q d
• end
• endmodule

S
Latch
D
Q
LE
R